| Patent application number | Description | Published |
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| 20100058073 | STORAGE SYSTEM, CONTROLLER, AND DATA PROTECTION METHOD THEREOF - A storage system including a storage unit, a connector, and a controller is provided. A personal identification number (PIN) message digest and a cipher text are stored in the storage unit. When the storage system is connected to a host system through the connector, the controller requests a password from the host system and generates a message digest through a one-way hash function according to the password. After that, the controller determinates whether the message digest matches the PIN message digest. If the message digest matches the PIN message digest, the controller decrypts the cipher text in the storage unit through a first encryption/decryption function according to the password to obtain an encryption/decryption key. Eventually, the controller encrypts and decrypts user data through a second encryption/decryption function according to the encryption/decryption key. Thereby, the user data stored in the storage system can be effectively protected. | 03-04-2010 |
| 20110145480 | FLASH MEMORY STORAGE SYSTEM FOR SIMULATING REWRITABLE DISC DEVICE, FLASH MEMORY CONTROLLER, COMPUTER SYSTEM, AND METHOD THEREOF - A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The controller configures a plurality of logical blocks and maps the logical blocks to a portion of the physical blocks. In addition, the controller identifies rewritable disc commands from the host system and writes data from the host system into the physical blocks mapped to the logical blocks according to the rewritable disc commands. Thereby, a rewritable disc device is simulated by using the flash memory storage system. | 06-16-2011 |
| Patent application number | Description | Published |
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| 20100044803 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 02-25-2010 |
| 20100109088 | BALANCE STEP-HEIGHT SELECTIVE BI-CHANNEL STRUCTURE ON HKMG DEVICES - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 05-06-2010 |
| 20110198675 | SPACER STRUCTURE OF A FIELD EFFECT TRANSISTOR - This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region. | 08-18-2011 |
| 20110237040 | MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 09-29-2011 |
| 20110278646 | Balance Step-Height Selective Bi-Channel Structure on HKMG Devices - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 11-17-2011 |
| 20120001259 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess. | 01-05-2012 |
| 20120009754 | METHOD FOR MAIN SPACER TRIM-BACK - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 01-12-2012 |
