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Ng, OR
Chun Kit Ng, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20080270958 | METHOD AND SYSTEM FOR DEBUG AND TEST USING REPLICATED LOGIC - A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded. This recorded data may then used to generate a test to be run on a software simulator when the circuit is modified. | 10-30-2008 |
| 20080301601 | TECHNIQUES FOR USE WITH AUTOMATED CIRCUIT DESIGN AND SIMULATIONS - Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described. | 12-04-2008 |
| 20080313578 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described. | 12-18-2008 |
| 20080313579 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described. | 12-18-2008 |
| 20080313589 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described. | 12-18-2008 |
| 20100122132 | METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC AND TRIGGER LOGIC - A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded. | 05-13-2010 |
Hein Tseong Ng, Beaverton, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090013436 | Generation of Plants with Altered Oil Content - The present invention is directed to plants that display an altered oil content phenotype due to altered expression of a HIO nucleic acid. The invention is further directed to methods of generating plants with an altered oil content phenotype. | 01-08-2009 |
Hein Tsoeng Ng, Beaverton, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20090162526 | Generation of plants with altered oil content - The present invention is directed to plants that display an altered oil content phenotype due to altered expression of a HIO1005 nucleic acid. The invention is further directed to methods of generating plants with an altered oil content phenotype. | 06-25-2009 |
| 20090282581 | GENERATION OF PLANTS WITH ALTERED OIL CONTENT - The present disclosure is directed to methods of generating plants with an altered oil content phenotype. | 11-12-2009 |
Pius Ng, Hllisboro, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20120017185 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit. | 01-19-2012 |
Pius Ng, Hillsboro, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20120017189 | ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION - Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
| 20120017198 | APPLICATION DRIVEN POWER GATING - Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
Plus Ng, Hillsboro, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20120017187 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
| 20120017196 | SYSTEM, ARCHITECTURE AND MICRO-ARCHITECTURE (SAMA) REPRESENTATION OF AN INTEGRATED CIRCUIT - Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement. | 01-19-2012 |
Yong-Gee Ng, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20120075938 | Adaptive and Dynamic Stability Enhancement for Memories - Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal. | 03-29-2012 |