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Nevers
Craig S. Nevers, Warwick, RI US
| Patent application number | Description | Published |
|---|---|---|
| 20110080750 | T-BAR MOUNTING SYSTEM - A T-bar mounting bracket assembly for a luminaire fixture frame having a bracket, a clip vertically adjustable relative to the bracket, the clip extending through an opening in the bracket, a fastener extending through the bracket and the clip and, the fastener spaced from a location where the clip passes through the opening. | 04-07-2011 |
Joseph G. Nevers, South Windsor, CT US
| Patent application number | Description | Published |
|---|---|---|
| 20090294610 | PICTURE HANGER ASSEMBLY AND METHOD - A support assembly to secure a stereo component to a wall includes a bracket secured to the component. The support assembly further includes a marking element that is received within an opening provided in the bracket. The marking element extends away from the component when positioning the marking element within the opening of the bracket. The arrangement is such that when positioning the marking element within the opening of the bracket, the marking element forms a mark on the wall in response to positioning the bracket against the wall. The support assembly further includes a fastener to secure the bracket to the wall. The fastener is received within the opening of the bracket so that the fastener is aligned with the mark on the wall. Other embodiments of the support assembly and methods of supporting components are further disclosed. | 12-03-2009 |
Yannick Marc Nevers, Grenoble FR
| Patent application number | Description | Published |
|---|---|---|
| 20100177544 | Generating ROM bit cell arrays - A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area. Thus the system designer can reuse an existing memory architecture, yet still retain an advantageous degree of flexibility with regard to performance characteristic selection of the final ROM bit cell array. | 07-15-2010 |
| 20110051487 | Read only memory cell for storing a multiple bit value - A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value. | 03-03-2011 |