| Patent application number | Description | Published |
|---|
| 20090060005 | Method for using a non-orthogonal pilot signal with data channel interference cancellation - A system and method for encoding/decoding data channels in a CDMA system having data channel interference cancellation, wherein data channel interference cancellation is used to remove unwanted non-orthogonal pilot signal components which are present within a demodulated data signal. This is accomplished by regenerating interference terms with respect to the non-orthogonal pilot signal and subtracting them from the demodulated data signal. | 03-05-2009 |
| 20090097455 | ACCESS CHANNEL STRUCTURE FOR WIRELESS COMMUNICATION SYSTEM - A technique for efficient implementation of pilot signals on a reverse link in a wireless communication system. An access channel is defined for the reverse link such that within each frame, or epoch, a portion is dedicated to sending only pilot symbols. Another portion of the frame is reserved for sending mostly data symbols; however, within this second portion of the frame, additional pilot symbols are interleaved among the data symbols. The pilot symbol or preamble portion of the access channel frame allows for efficient acquisition of the access signal at the base station, while providing a timing reference for determining the effects of multipath fading. In particular, a pilot correlation filter provides a phase estimate from the pilot symbols in the preamble portion, which is then used to decode the data symbols in the payload portion. An access acquisition portion of the receiver uses the phase estimates provided by the pilot correlation filter to process the output of a data symbol correlation filter. The additional pilot symbols embedded in the payload portion are used in a cross product operation to further resolve the effects of multipath fading. | 04-16-2009 |
| 20090116469 | Reverse link pilot integrated with block codes - A technique for encoding digital communication signals. Data symbols are augmented in pilot symbols inserted at predetermined positions. The pilot augmented sequence is then fed to a deterministic error correction block encoder, such as a turbo product coder, to output a coded sequence. The symbols in the error correction encoded sequence are then rearranged to ensure that the output symbols derived from input pilot symbols are located at regular, predetermined positions. As a result, channel encoding schemes can more easily be used which benefits from power of two length block sizes. | 05-07-2009 |
| 20090135950 | MAXIMIZING DATA RATE BY ADJUSTING CODES AND CODE RATES - The present invention provides for making code rate adjustments and modulation type adjustments in a pseudonoise (PN) encoded CDMA system. Coding rate adjustments may be made by changing the number of information bits per symbol, or Forward Error Code (FEC) coding rate. A forward error correction (FEC) block size is maintained at a constant amount. Therefore, as the number of information bits per symbol are increased, an integer multiple of bits per epoch is always maintained. The scheme permits for a greater flexibility and selection of effective data rates providing information bit rates ranging from, for example, approximately 50 kilobits per second to over 5 mega bits per second (Mbps) in one preferred embodiment. | 05-28-2009 |
| 20090225718 | TECHNIQUES FOR SETTING UP TRAFFIC CHANNELS IN A COMMUNICATIONS SYSTEM - A control channel supporting traffic control in epochs is divided into two control subchannels each being less than or equal to about a half epoch in duration and occurring serially in time. Slot allocation data may be transmitted and received independently over the subchannels. One subchannel may be used for transmitting forward slot allocation data and the other subchannel may be used for transmitting reverse slot allocation data. The channel split into two subchannels may be a paging channel. The forward and reverse slot allocation data may be transmitted between a base station processor and field unit. Forward and reverse traffic data may be staggered by at least about half an epoch. Transmission of traffic data happens within about two epochs after the assignments. | 09-10-2009 |
| 20100208612 | Method for Mitigating Adverse Processor Loading in a Personal Computer Implementation of a Wireless Local Area Network Adapter - A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the polling mechanism associated with the power save (PS) functionality of WLAN protocol to relieve networking stress on the host processing system. It does this while maintaining networking integrity and packet delivery. The WLAN protocol polling mechanism is used to briefly inhibit the transfer of packets from the WLAN access point (AP) during peak periods of network traffic and/or host processor loading. Because the modulation, demodulation, and MAC functions, typically implemented in dedicated hardware on existing adapters are implemented in software running on the host PC microprocessor, other host system processes and applications can interfere with these time critical functions. Conversely, latency introduced by WLAN specific processing tasks during peak periods of network traffic may cause unacceptable delays to the other processes and applications requiring microprocessor attention. In addition to its primary stated purpose of allowing WLAN mobile stations to save power, this technique will use power save polling as a method for controlling delivery of network packets when the host is heavily loaded or when peak interrupt latencies make reliable packet delivery difficult or impossible. | 08-19-2010 |
| 20120087364 | REVERSE LINK PILOT INTEGRATED WITH BLOCK CODES - A technique for encoding digital communication signals. Data symbols are augmented in pilot symbols inserted at predetermined positions. The pilot augmented sequence is then fed to a deterministic error correction block encoder, such as a turbo product coder, to output a coded sequence. The symbols in the error correction encoded sequence are then rearranged to ensure that the output symbols derived from input pilot symbols are located at regular, predetermined positions. As a result, channel encoding schemes can more easily be used which benefits from power of two length block sizes. | 04-12-2012 |
