Patent application number | Description | Published |
20090251957 | SYSTEM AND METHOD FOR WRITING DATA TO MAGNETORESISTIVE RANDOM ACCESS MEMORY CELLS - Magnetic random access memory (MRAM) cell with a thermally assisted switching writing procedure and methods for manufacturing and using same. The MRAM cell includes a magnetic tunnel junction that has at least a first magnetic layer, a second magnetic layer, and an insulating layer disposed between the first and a second magnetic layers. The MRAM cell further includes a select transistor and a current line electrically connected to the junction. The current line advantageously can support a plurality of MRAM operational functions. The current line can fulfill a first function for passing a first portion of current for heating the junction and a second function for passing a second portion of current in order to switch the magnetization of the first magnetic layer. | 10-08-2009 |
20090316476 | SHARED LINE MAGNETIC RANDOM ACCESS MEMORY CELLS - A memory unit with one field line; at least two thermally-assisted switching magnetic tunnel junction-based magnetic random access memory cells, each cell comprising a magnetic tunnel junction having an insulating layer disposed between a magnetic storage layer and a magnetic reference layer; wherein a selection transistor is connected to the magnetic tunnel junction; the one field line is used for passing a field current for switching a magnetization of the storage layer of the magnetic tunnel junctions of the cells. A magnetic memory device can be formed by assembling an array of the memory units, wherein at least two adjacent magnetic tunnel junctions of the cells can be addressed simultaneously by the field line. The memory unit and magnetic memory device have a reduced surface area. Magnetic memory devices with an increased density of memory units can be fabricated resulting in lower die fabrication cost and lower power consumption. | 12-24-2009 |
20100302832 | NON-VOLATILE LOGIC DEVICES USING MAGNETIC TUNNEL JUNCTIONS - The present disclosures concerns a register cell comprising a differential amplifying portion containing a first inverter coupled to a second inverter such as to form an unbalanced flip-flop circuit; a first and second bit line connected to one end of the first and second inverter, respectively; and a first and second source line connected to the other end of the first and second inverter, respectively; characterized by the register cell further comprising a first and second magnetic tunnel junction electrically connected to the other end of the first and second inverter, respectively. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. | 12-02-2010 |
20110007561 | SELF-REFERENCED MAGNETIC RANDOM ACCESS MEMORY CELLS - The present disclosure concerns a magnetic random access memory cell containing a magnetic tunnel junction formed from an insulating layer comprised between a sense layer and a storage layer. The present disclosure also concerns a method for writing and reading the memory cell comprising, during a write operation, switching a magnetization direction of said storage layer to write data to said storage layer and, during a read operation, aligning magnetization direction of said sense layer in a first aligned direction and comparing said write data with said first aligned direction by measuring a first resistance value of said magnetic tunnel junction. The disclosed memory cell and method allow for performing the write and read operations with low power consumption and an increased speed. | 01-13-2011 |
20110216580 | MRAM-BASED MEMORY DEVICE WITH ROTATED GATE - A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor; a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor; wherein the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and wherein each source line connecting the MRAM cells via the other end of the magnetic tunnel junction. | 09-08-2011 |
20120008380 | METHOD FOR WRITING IN A MRAM-BASED MEMORY DEVICE WITH REDUCED POWER CONSUMPTION - A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption. | 01-12-2012 |
20120143554 | Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine Based On Flash Cells - A check engine includes a plurality of comparators, each including a plurality of flash cells, where each of the plurality of comparators is configured to store at least one reference bit included in a set of reference bits, and includes an input for presenting at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators. | 06-07-2012 |
20120143889 | Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine - A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators. | 06-07-2012 |
20120201073 | Memory Devices with Series-Interconnected Magnetic Random Access Memory Cells - A memory device includes magnetic random access memory (“MRAM”) cells that are electrically connected in series, each one of the MRAM cells having a storage magnetization direction and a sense magnetization direction. During a write operation, multiple ones of the MRAM cells are written in parallel by switching the storage magnetization directions of the MRAM cells. During a read operation, a particular one of the MRAM cells is read by varying the sense magnetization direction of the particular one of the MRAM cells, relative to the storage magnetization direction of the particular one of the MRAM cells. | 08-09-2012 |
20120201074 | Magnetic Random Access Memory Devices Configured for Self-Referenced Read Operation - A magnetic random access memory cell includes a sense layer, a storage layer, and a spacer layer disposed between the sense layer and the storage layer. During a write operation, the storage layer has a magnetization direction that is switchable between m directions to store data corresponding to one of m logic states, with m>2. During a read operation, the sense layer has a magnetization direction that is varied, relative to the magnetization direction of the storage layer, to determine the data stored by the storage layer. | 08-09-2012 |
20120314487 | Magnetic Random Access Memory Devices Including Multi-Bit Cells - A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The MRAM cell also includes a field line magnetically coupled to the MRAM cell and configured to induce a write magnetic field along a magnetic field axis, and the magnetic anisotropy axis is tilted relative to the magnetic field axis. During a write operation, the first magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. | 12-13-2012 |
20120314488 | Magnetic Random Access Memory Devices Including Multi-Bit Cells - A magnetic random access memory (MRAM) cell includes a storage layer, a sense layer, and a spacer layer between the storage layer and the sense layer. A field line is magnetically coupled to the MRAM cell to induce a magnetic field along a magnetic field axis, and at least one of the storage layer and the sense layer has a magnetic anisotropy axis that is tilted relative to the magnetic field axis. During a write operation, a storage magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, where at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis. During a read operation, a sense magnetization direction is varied, relative to the storage magnetization direction, to determine the data stored by the storage layer. | 12-13-2012 |
20130070520 | Magnetic Random Access Memory Devices Including Shared Heating Straps - A memory device includes: (1) multiple magnetic random access memory (“MRAM”) cells each including a first end and a second end; (2) a bit line electrically coupled to the first end of at least one of the MRAM cells; and (3) a strap electrically coupled to the second end of each one of the MRAM cells. During a write operation, the bit line is configured to apply a first heating current, and the strap is configured to apply a second heating current, such that at least one of the MRAM cells is heated to at least a threshold temperature according to the first heating current and the second heating current. | 03-21-2013 |
20130070521 | Magnetic Random Access Memory Devices Including Heating Straps - A memory device includes at least one magnetic random access memory cell, which includes: (1) a magnetic tunnel junction having a first end and a second end; and (2) a strap electrically coupled to the second end of the magnetic tunnel junction. The memory device also includes a bit line electrically coupled to the first end of the magnetic tunnel junction. During a write operation, the bit line is configured to apply a first heating current through the magnetic tunnel junction, and the strap is configured to apply a second heating current through the strap, such that the magnetic tunnel junction is heated to at least a threshold temperature according to the first heating current and the second heating current. | 03-21-2013 |
20130094283 | Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line - A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity. | 04-18-2013 |
20140110802 | Memory Devices with Magnetic Random Access Memory (MRAM) Cells and Associated Structures for connecting the MRAM Cells - A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap. | 04-24-2014 |
20140195883 | Apparatus, System, and Method for Matching Patterns with an Ultra Fast Check Engine - A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators. | 07-10-2014 |
20140269042 | Self-referenced Magnetic Random Access Memory - The present disclosure concerns a magnetic random access memory cell containing a magnetic tunnel junction formed from an insulating layer comprised between a sense layer and a storage layer. The present disclosure also concerns a method for writing and reading the memory cell comprising, during a write operation, switching a magnetization direction of said storage layer to write data to said storage layer and, during a read operation, aligning magnetization direction of said sense layer in a first aligned direction and comparing said write data with said first aligned direction by measuring a first resistance value of said magnetic tunnel junction. The disclosed memory cell and method allow for performing the write and read operations with low power consumption and an increased speed. | 09-18-2014 |
20140361392 | Memory Devices with Magnetic Random Access Memory (MRAM) Cells and Associated Structures for Connecting the MRAM Cells - A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap. | 12-11-2014 |