Patent application number | Description | Published |
20110023068 | METHOD AND SYSTEM TO SEARCH VIEWABLE CONTENT - A system to search to search viewable content in the context of television entertainment is provided. In one example embodiment, the system comprises a communications module to receive a request associated with one or more directional keys on a control device, a search term detector to determine a search term associated with the request, a search module to locate a content item associated with the search term; and a presentation module to present the content item associated with the search term. | 01-27-2011 |
20110090402 | METHOD AND SYSTEM TO NAVIGATE VIEWABLE CONTENT - A method and system to navigate viewable content in the context of television entertainment is provided. In one example embodiment, the system comprises a presentation module to present main content on a display screen, a communications module to receive a first request associated with a first directional key on a remote control device, a navigation mode detector to determine a navigation mode associated with the first request; a margin menu module to activate a margin menu associated with the determined navigation mode. The margin menu may be presented along one of the margins of a display screen, while permitting viewing of the main content. | 04-21-2011 |
20140245357 | METHOD AND SYSTEM TO NAVIGATE VIEWABLE CONTENT - A method and system to navigate viewable content in the context of television entertainment is provided. In one example embodiment, the system comprises a presentation module to present main content on a display screen, a communications module to receive a first request associated with a first directional key on a remote control device, a navigation mode detector to determine a navigation mode associated with the first request; a margin menu module to activate a margin menu associated with the determined navigation mode. The margin menu may be presented along one of the margins of a display screen, while permitting viewing of the main content. | 08-28-2014 |
Patent application number | Description | Published |
20080219055 | MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE - The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels. | 09-11-2008 |
20090010064 | NAND FLASH CELL STRUCTURE - NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode floating gate memory cells allow for increased cell current through lower channel r | 01-08-2009 |
20090073765 | NON-VOLATILE MEMORY DEVICE AND METHOD HAVING BIT-STATE ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 03-19-2009 |
20090154247 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-18-2009 |
20100142280 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 06-10-2010 |
20100172175 | MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 07-08-2010 |
20100302844 | METHOD AND APPARATUS FOR PROVIDING A NON-VOLATILE MEMORY WITH REDUCED CELL CAPACITIVE COUPLING - A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling. | 12-02-2010 |
20120039123 | MULTIPLE LEVEL PROGRAMMING IN A NON-VOLATILE MEMORY DEVICE - The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels. | 02-16-2012 |
20120057404 | MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 03-08-2012 |
20120221779 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 08-30-2012 |
20130141981 | MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING - A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row. | 06-06-2013 |