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| 20110099258 | Dynamic Control of Autonomic Management of a Data Center - A method, system, and article for autonomizing autonomic management of a data center, with the data center having at least one computer system and an associated component. Data is collected from the data center and used as input to identify a data center policy. A set of capabilities of elements of the data center are detected and cataloged based upon the collected data. At least one policy is dynamically selected from at least one set of master policies in a policy directory with the selected policy to support the cataloged capabilities of the data center, and to dynamically control selective application and to adapt parameters for quality of service. The selected policy is applied to manage the data center. | 04-28-2011 |
| 20110113295 | SUPPORT ELEMENT OFFICE MODE ARRAY REPAIR CODE VERIFICATION - A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution. | 05-12-2011 |
| 20110196957 | Real-Time Policy Visualization by Configuration Item to Demonstrate Real-Time and Historical Interaction of Policies - Multiple policy engines may be integrated with a change and configuration change database to enable coordination of multiple policies by an embodiment comprising: a data center having a plurality of configuration items and connected to a network; a database connected to the network; a plurality of policy engines connected to the network; wherein each of the plurality of policy engines is configured to apply one or more policies to the data center in accordance with an awareness of all configuration item changes made by all other policy engines connected to the network; wherein the awareness comprises a plurality of relationships, each relationship being between a policy data and a configuration item. | 08-11-2011 |
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| 20090114912 | MASK DESIGN ELEMENTS TO AID CIRCUIT EDITING AND MASK REDESIGN - An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing. | 05-07-2009 |
| 20100225367 | FREQUENCY SYNTHESIZER WITH IMMUNITY FROM OSCILLATOR PULLING - Frequency synthesizer with immunity from oscillator pulling. The frequency synthesizer for generating an output frequency includes an oscillator that is capable of generating a first frequency. The frequency synthesizer also includes an output divider coupled to the oscillator. The output divider is configurable to allow the oscillator to generate a second frequency to prevent degradation in phase noise due to an interference to the first frequency of the oscillator, and to generate the output frequency from the second frequency. | 09-09-2010 |
| 20110053537 | FREQUENCY MODULATION RECEIVER WITH A LOW POWER FREQUENCY SYNTHESIZER - A frequency modulation (FM) receiver with a low power frequency synthesizer. A FM receiver includes a low noise amplifier for processing a received input signal, a frequency synthesizer having an oscillator for generating a local oscillator signal by supplying a bias current to the oscillator, and a mixer for generating an intermediate frequency signal by mixing the received input signal with the local oscillator signal. The FM receiver further includes an analog to digital converter for converting the intermediate frequency signal to a digital signal and a bias current control module for measuring a signal strength of the received input signal based on the digital signal and for controlling the bias current. | 03-03-2011 |
| 20110084771 | Low Phase Noise Frequency Synthesizer - Various apparatuses and methods for a low phase noise frequency synthesizer are disclosed herein. For example, some embodiments provide an oscillator that may be used in a low phase noise frequency synthesizer. The oscillator includes a tank circuit, a plurality of cross-coupled transistor pairs connected to the tank circuit, a current source connected to the plurality of cross-coupled transistor pairs, and at least one switch connected to the plurality of cross-coupled transistor pairs. The switch is adapted to activate a subset of the plurality of cross-coupled transistor pairs and to deactivate another subset of the plurality of cross-coupled transistor pairs to operate the tank circuit in the oscillator using the activated subset of the plurality of cross-coupled transistor pairs. | 04-14-2011 |
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| 20090009206 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively. A second multiplexer selects a reference data input bit that corresponds to one of the internal data strobe input signals of the input/output bit pair signals s from the delay line blocks and a third multiplexer for selecting a reference data output bit that corresponds to one of the phase shifted data strobe output signals from the input/output bit pair signals. A phase detector for determining a phase difference between the reference data input bit and the reference data output bit and outputting a phase difference value. | 01-08-2009 |
| 20090013228 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively. A second multiplexer selects a reference data input bit that corresponds to one of the internal data strobe input signals of the input/output bit pair signals s from the delay line blocks and a third multiplexer for selecting a reference data output bit that corresponds to one of the phase shifted data strobe output signals from the input/output bit pair signals. A phase detector for determining a phase difference between the reference data input bit and the reference data output bit and outputting a phase difference value. | 01-08-2009 |
| 20110026343 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value. | 02-03-2011 |
| 20110176374 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value. | 07-21-2011 |
