Patent application number | Description | Published |
20100074078 | Systems and Methods for Low Latency Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value. | 03-25-2010 |
20100208574 | Systems and Methods for Reduced Latency Loop Recovery - Various embodiments of the present invention provide systems and methods for reduced latency feedback in a data processing system. For example, some embodiments provide a data processing system that includes a variable gain amplifier, a processing circuit, a data detector, and an error signal calculation circuit. The variable gain amplifier amplifies a data input signal and provides an amplified signal. The processing circuit generates a signal output corresponding to the amplified signal, and includes a conditional multiplication circuit. The conditional multiplication circuit conditionally multiplies the signal output by a gain correction signal and provides the result as an interim output. The data detector applies a data detection algorithm to the signal output and provides an ideal output. The error signal calculation circuit generates a gain correction signal based at least in part on the interim output and a derivative of the ideal output. The level of amplification by the variable gain amplifier is based at least in part on the gain correction signal. | 08-19-2010 |
20100226031 | Systems and Methods for Defective Media Region Identification - Various embodiments of the present invention provide systems and methods for storage medium flaw detection. For example, some embodiments provide flaw detection systems that include an input circuit, a data processing circuit and a defect detection circuit. The input circuit is operable to receive an input signal and to provide a filtered output. The data processing circuit is operable to receive the filtered output and to compute a difference between the filtered output and an expected output, and the defect detection circuit receives the difference between the filtered output and the expected output and compares a derivative of the difference with a threshold value, and asserts a defect signal when a magnitude of the derivative of the difference exceeds a threshold value. | 09-09-2010 |
20100329096 | Systems and Methods for Hard Disk Drive Data Storage Including Reduced Latency Loop Recovery - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes a summation circuit, a data detector circuit, an error feedback circuit, and an error calculation circuit. The summation circuit subtracts a low frequency offset feedback from an input signal to yield a processing output. The data detector circuit applies a data detection algorithm to a derivative of the processing output and provides an ideal output. The error feedback circuit includes a conditional subtraction circuit that conditionally subtracts an interim low frequency offset correction signal from a delayed version of the derivative of the processing output to yield an interim factor. The error calculation circuit generates an interim low frequency offset correction signal based at least in part on the interim factor and a derivative of the ideal output. In such embodiments, the low frequency offset feedback is derived from the interim low frequency offset correction signal. | 12-30-2010 |
20110002211 | Systems and Methods for Format Efficient Timing Recovery In a Read Channel - Various embodiments of the present invention provide systems, methods and media formats for processing user data derived from a storage medium. As an example, a system is described that includes a storage medium with a series of data. The series of data includes a servo data and a user data region. The user data region includes a first synchronization pattern and a second synchronization pattern located a distance from the first synchronization pattern. A storage buffer is provided that is operable to receive at least a portion of the series of data. A retiming circuit calculates an initial phase offset and frequency offset for a defined bit within the storage buffer using a first location of the first synchronization pattern and a second location of the second synchronization pattern. An error correction loop circuit re-samples the series of data from the storage buffer based at least in part on the initial phase offset and a frequency offset. | 01-06-2011 |
20110018748 | Systems and Methods for Two Tier Sampling Correction in a Data Processing Circuit - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value. | 01-27-2011 |
20110063746 | Systems and Methods for Improved Servo Data Operation - Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker. The interpolation circuit is operable to interpolate the position location data and to provide an interpolated position location data. | 03-17-2011 |
20120019946 | Systems and Methods for Adaptive Baseline Compensation - Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, some embodiments provide data processing circuits that include: an input circuit, a processing circuit, a data detection circuit, and a baseline compensation circuit. The input circuit receives a first data input and provides a second data input. The input circuit excludes low frequency energy exhibited in the first data input from the second data input. The processing circuit generates a representation of the second data input, and the data detection circuit generates a representation of the first data input based at least in part on the representation of the second data input. The baseline compensation circuit calculates an accumulated difference between the representation of the first data input and the representation of the second data input across a number of bit periods, and calculates a compensation factor based at least in part on the accumulated difference. | 01-26-2012 |
20130205185 | Systems and Methods for Low Latency Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value. | 08-08-2013 |