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Naveen
Naveen Aerrabotu, Gurnee, IL US
| Patent application number | Description | Published |
|---|---|---|
| 20080207166 | Method and Apparatus for Providing a Data Protocol Voice Enabled Subscription Lock for a Wireless Communication Device - A method and system for restricting at least partial usage of a wireless communication device ( | 08-28-2008 |
| 20090134836 | DEVICES AND METHODS FOR ELECTRONIC DEVICE RECHARGING - Disclosed are devices and methods for regulating providing a charge via a charge receiving port of one device, the one device coupled to another device having a charge providing port. In one embodiment, the ports can be coupled by a cable. In another embodiment, the ports can be coupled wirelessly. The charge delivering device may regulate a charge providing process, controlled by a charge regulating controller of the charge providing device and based, for example, upon predetermined criteria. A charge regulating controller can disable the charging process, monitor the charge depletion rate, or the charging process may be based upon user established criteria. A charge regulating controller of the other device can regulate the charge accepting process. Each device may take on both roles, that is providing charge and receiving charge. | 05-28-2009 |
| 20100159955 | Method and Apparatus for Providing Location-Based Information - A method and apparatus for providing location-based information to a wireless communication device is disclosed. The wireless communication device receives its geographic position information and provides its geographic position information to a web server while accessing a web service provided by the web server. Based on the geographic position information received from the wireless communication device, the web server provides geographic coordinates of locations relevant to the web service in the form of web geo-cookies. The wireless communication device maintains a database of the received geographic coordinates. When the wireless communication accesses a geographic map of a route or region, the wireless communication device determines if the geographic coordinates in the database lie within boundaries of the accessed map. The geographic coordinates that lie within boundaries of the received map are annotated and displayed on the wireless communication device. | 06-24-2010 |
Naveen Balani, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20110022663 | Partially and Completely Duplicative Messages Handling - A first queue stores messages to be consumed. A second queue temporarily stores completely duplicative messages that have message identifiers equal to message identifiers of messages currently being processed s and that have times equal to times of the messages being processed; processing of the completely duplicative messages never occurs. By comparison, a partially duplicative message has its processing delayed until the message of which it is partially duplicative has been finished being processed. A partially duplicative message has a message identifier equal to a message identifier of a message referenced within the non-persistent store and has a time unequal to a time of the message referenced within the non-persistent store is moved from the first to the second queue. A non-persistent store stores references to the messages currently being processed. Once the messages are finished being processed, the references to them are removed from the non-persistent store. | 01-27-2011 |
Naveen Bhoria, Plano, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20120079102 | Requester Based Transaction Status Reporting in a System with Multi-Level Memory - A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed. | 03-29-2012 |
| 20120079155 | Interleaved Memory Access from Multiple Requesters - A shared memory system having multiple banks is coupled to a set of requesters. Separate arbitration and control logic is provided for each bank, such that each bank can be accessed individually. The separate arbitration logics individually arbitrate transaction requests targeted to each bank of the memory. Access is granted to each bank on each access cycle to a highest priority request for each bank, such that more than one transaction request may be granted access to the memory on a same access cycle. A wide transaction request that has a transaction width that is wider than a width of one bank is divided into a plurality of divided requests. | 03-29-2012 |
Naveen Candrasekaran, Rolla, MO US
| Patent application number | Description | Published |
|---|---|---|
| 20110250428 | PREPARATION OF CROSS-LINKED AEROGELS AND DERIVATIVES THEREOF - Three-dimensional nanoporous aerogels and suitable preparation methods are provided. Nanoporous aerogels may include a carbide material such as a silicon carbide, a metal carbide, or a metalloid carbide. Elemental (e.g., metallic or metalloid) aerogels may also be produced. In some embodiments, a cross-linked aerogel having a conformal coating on a sol-gel material is processed to form a carbide aerogel, metal aerogel, or metalloid aerogel. A three-dimensional nanoporous network may include a free radical initiator that reacts with a cross-linking agent to form the cross-linked aerogel. The cross-linked aerogel may be chemically aromatized and chemically carbonized to form a carbon-coated aerogel. The carbon-coated aerogel may be suitably processed to undergo a carbothermal reduction, yielding an aerogel where oxygen is chemically extracted. Residual carbon remaining on the surface of the aerogel may be removed via an appropriate cleaning treatment. | 10-13-2011 |
Naveen Dakappagari, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120107301 | METHOD OF TREATING AUTOIMMUNE DISEASE BY INDUCING ANTIGEN PRESENTATION BY TOLERANCE INDUCING ANTIGEN PRESENTING CELLS - Antibodies to antigen presenting cells may be utilized to interfere with the interaction of the antigen presenting cell and immune cells, including T cells. Peptides may be linked to said antibodies thereby generating an immune response to such peptides. Preferably peptides linked to the antibodies are associated with autoimmunity. | 05-03-2012 |
Naveen Gundubogula, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110110174 | System and Method of Operating a Memory Device - A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal. | 05-12-2011 |
Naveen Gunukula, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100142368 | FAILOVER AND FAILBACK OF COMMUNICATION BETWEEN A ROUTER AND A NETWORK SWITCH - A router is provided. The router includes a primary interface, a backup interface, a processor, and a memory. The primary interface and backup interface may be used to communicate with a network switch. The router may be configured to determine whether the primary interface is stable. The primary interface is stable when the primary interface may be used to exchange information with a network switch over a primary network segment. The router may be configured to activate the primary interface when the primary interface is determined to be stable. The router may also be configured to activate the backup interface when the primary interface is determined to be not stable. The backup interface may be activated for the exchange of information with the network switch. | 06-10-2010 |
Naveen Gunukula, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120057452 | FAILOVER AND FAILBACK OF COMMUNICATION BETWEEN A ROUTER AND A NETWORK SWITCH - A router is provided. The router includes a primary interface, a backup interface, a processor, and a memory. The primary interface and backup interface may be used to communicate with a network switch. The router may be configured to determine whether the primary interface is stable. The primary interface is stable when the primary interface may be used to exchange information with a network switch over a primary network segment. The router may be configured to activate the primary interface when the primary interface is determined to be stable. The router may also be configured to activate the backup interface when the primary interface is determined to be not stable. The backup interface may be activated for the exchange of information with the network switch. | 03-08-2012 |
Naveen Gupta, Ann Arbor, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20090175736 | SYSTEM AND METHOD FOR PROVIDING A THERMAL TRANSPIRATION GAG PUMP USING A NANOPOROUS CERAMIC MATERIAL - A system and method for using an element made of porous ceramic materials such as zeolite to constrain the flow of gas molecules to the free molecular or transitional flow regime. A preferred embodiment of the gas pump may include the zeolite element, a heater, a cooler, passive thermal elements, and encapsulation. The zeolite element may be further comprised of multiple types of porous matrix sub-elements, which may be coated with other materials and may be connected in series or in parallel. The gas pump may further include sensors and a control mechanism that is responsive to the output of the sensors. The control mechanism may further provide the ability to turn on and off certain heaters in order to reverse the flow in the gas pump. In one embodiment, the pump may operate by utilizing waste heat from an external system to induce transpiration driven flow across the zeolite. In another embodiment, the pump may selectively drive and direct gas molecules depending on the molecular size and the interaction between the gas molecule and the zeolite element. | 07-09-2009 |
Naveen Javarappa, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090174458 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 07-09-2009 |
| 20110032020 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 02-10-2011 |
| 20110255351 | Level Shifter with Embedded Logic and Low Minimum Voltage - In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations. | 10-20-2011 |
Naveen Kachroo, Redmond, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20090024522 | SYSTEM AND METHOD PROVIDING RULES DRIVEN SUBSCRIPTION EVENT PROCESSING - The present invention relates to a system and methodology providing an automated and dynamically responsive infrastructure to support online subscription services. The system includes one or more components to coordinate and manage a plurality of services offered by multiple service providers. This can include automatically creating and managing billing accounts for customers subscribing to such services. At least one engine is provided to process multiple rules in response to subscription events that occur in connection with the services in order to facilitate service delivery. At least one rating processor is provided to process multiple rating rules in response to subscription events for currency and non-currency resources. | 01-22-2009 |
Naveen Kashyap, Singapore SG
| Patent application number | Description | Published |
|---|---|---|
| 20100191568 | APPARATUS AND METHOD FOR MANAGING TASK INFORMATION OF A PLANT - An apparatus for managing task information of a plant, the plant being controlled by a control system and configured to be operated in shifts. The apparatus comprises a server for automatically obtaining and storing information from a current work shift of the plant from the control system; and at least one client connected to the server and comprising a logbook application module for manipulating the obtained information. Preferably, the server is configured to automatically transmit manipulated information to identified users of a subsequent work shift. | 07-29-2010 |
Naveen Matam, Rancho Cordova, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080307202 | LOADING TEST DATA INTO EXECUTION UNITS IN A GRAPHICS CARD TO TEST THE EXECUTION UNITS - Provided are a method and system for loading test data into execution units in a graphics card to test the execution units. Test instructions are loaded into a cache in a graphics module comprising multiple execution units coupled to the cache on a bus during a design test mode. The cache instructions are concurrently transferred to an instruction queue of each execution unit to concurrently load the cache instructions into the instruction queues of the execution units. The execution units concurrently execute the cache instructions to fetch test instructions from the cache to load into memories of the execution units and execute during the design test mode. | 12-11-2008 |
Naveen Maveli, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090083537 | SERVER CONFIGURATION SELECTION FOR SSL INTERCEPTION - A network intermediary device such as a transaction accelerator intercepts a client request for a secure communication connection with a server. The intermediary issues a substitute connection request to the server and receives a digital certificate during establishment of a secure communication session between the intermediary and the server. Based on information in the received digital certificate, the intermediary selects an appropriate operational configuration for responding to the client's request. The intermediary consults an ordered list or other collection of digital certificates it possesses, and chooses one having a common name that matches the server's common name. The match may comprise the first matching name, the longest match, the best match, the broadest match (e.g., a certificate having a name that includes one or more wildcard characters), etc. The intermediary then uses the selected certificate (and corresponding private key) to establish a secure communication session with the client. | 03-26-2009 |
| 20090083538 | REDUCING LATENCY OF SPLIT-TERMINATED SECURE COMMUNICATION PROTOCOL SESSIONS - A method is provided for establishing a split-terminated secure communication connection between a client and a server. A first network intermediary intercepts a secure communication connection request directed from the client to the server. A second intermediary having a digital certificate in the name of the server (and a corresponding private key) acts in place of the server to establish a first secure communication session with the client, during which it receives a secret from the client for generating the session key. The second intermediary supplies the secret and/or the session key to the first intermediary, which allows the first intermediary to establish follow-on secure communication sessions in which the secret is reused. The second intermediary may also supply the first intermediary with a copy of its certificate so that it can respond to new secure communication requests and, yet further, may also supply a copy of the private key. | 03-26-2009 |
Naveen Muralimanohar, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110119525 | CHECKPOINTING IN MASSIVELY PARALLEL PROCESSING - One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory. | 05-19-2011 |
| 20110246828 | Memory Checkpointing Using A Co-Located Processor and Service Processor - A system and method is shown that includes a processor operatively connected to a memory, the processor to include a memory controller to control access to the memory. The system and method also includes a service processor, co-located on a common board and operatively connected to the processor and the memory, the service processor to include an additional memory controller to control access to the memory as part of a checkpoint regime. | 10-06-2011 |
| 20120017065 | PARALLELIZED CHECK POINTING USING MATs AND THROUGH SILICON VIAs (TSVs) - A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs. | 01-19-2012 |
Naveen Neelakantam, Urbana, IL US
| Patent application number | Description | Published |
|---|---|---|
| 20080244544 | Using hardware checkpoints to support software based speculation - Hardware checkpoints may be used to mark software-based speculation regions. An instruction may be provided at the beginning of a speculation region and at the end of the speculation region. If an exception occurs during the speculation region, a hardware rollback may be occurred. The hardware rollback rolls back to the instruction at the beginning of the speculation region. The hardware may take a checkpoint by taking a register snapshot and treating future memory updates as tentative. When the instruction marking the end of the speculation is reached, all the tentative memory updates are committed and the previously taken register snapshot is discarded. | 10-02-2008 |
Naveen Thumpudi, Redmond, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20120035941 | QUANTIZATION AND INVERSE QUANTIZATION FOR AUDIO - An audio encoder and decoder use architectures and techniques that improve the efficiency of quantization (e.g., weighting) and inverse quantization (e.g., inverse weighting) in audio coding and decoding. The described strategies include various techniques and tools, which can be used in combination or independently. For example, an audio encoder quantizes audio data in multiple channels, applying multiple channel-specific quantizer step modifiers, which give the encoder more control over balancing reconstruction quality between channels. The encoder also applies multiple quantization matrices and varies the resolution of the quantization matrices, which allows the encoder to use more resolution if overall quality is good and use less resolution if overall quality is poor. Finally, the encoder compresses one or more quantization matrices using temporal prediction to reduce the bitrate associated with the quantization matrices. An audio decoder performs corresponding inverse processing and decoding. | 02-09-2012 |
| 20120082316 | MULTI-CHANNEL AUDIO ENCODING AND DECODING - An audio encoder and decoder use architectures and techniques that improve the efficiency of multi-channel audio coding and decoding. The described strategies include various techniques and tools, which can be used in combination or independently. For example, an audio encoder performs a pre-processing multi-channel transform on multi-channel audio data, varying the transform so as to control quality. The encoder groups multiple windows from different channels into one or more tiles and outputs tile configuration information, which allows the encoder to isolate transients that appear in a particular channel with small windows, but use large windows in other channels. Using a variety of techniques, the encoder performs flexible multi-channel transforms that effectively take advantage of inter-channel correlation. An audio decoder performs corresponding processing and decoding. In addition, the decoder performs a post-processing multi-channel transform for any of multiple different purposes. | 04-05-2012 |
| 20120087504 | MULTI-CHANNEL AUDIO ENCODING AND DECODING - An audio encoder and decoder use architectures and techniques that improve the efficiency of multi-channel audio coding and decoding. The described strategies include various techniques and tools, which can be used in combination or independently. For example, an audio encoder performs a pre-processing multi-channel transform on multi-channel audio data, varying the transform so as to control quality. The encoder groups multiple windows from different channels into one or more tiles and outputs tile configuration information, which allows the encoder to isolate transients that appear in a particular channel with small windows, but use large windows in other channels. Using a variety of techniques, the encoder performs flexible multi-channel transforms that effectively take advantage of inter-channel correlation. An audio decoder performs corresponding processing and decoding. In addition, the decoder performs a post-processing multi-channel transform for any of multiple different purposes. | 04-12-2012 |
Naveen Thuramalla, Ithaca, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080275354 | System and method for diverting flow to facilitate measurement of system parameters - A method and various devices are disclosed that facilitates the measurement of hemodynamic parameters by injection of an indicator in an indicator dilution technique using an extracorporeal circuit connected to a patient. Specifically, the invention deals with problems caused by the spike in pressure in an extracorporeal line that result from the injection of a bolus. The method and various devices provide for diversion of blood during an indictor injection process and then return of the diverted blood back into the system after the injection is completed. The variations of the invention use diversion lines, accommodating cases and other devices that are designed to accumulate blood displaced during injection and then returning the blood to the extracorporeal circuit after injection. | 11-06-2008 |
Naveen Tipirneni, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110095359 | Field Boosted Metal-Oxide-Semiconductor Field Effect Transistor - A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions. | 04-28-2011 |
Naveen Tipirneni, Milpitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090090984 | Novel Method to Increase Breakdown Voltage of Semiconductor Devices - Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN. | 04-09-2009 |
Naveen Tumula, Lake Zurich, IL US
| Patent application number | Description | Published |
|---|---|---|
| 20120025728 | HID LAMP IGNITOR - An HID lamp ignitor for a lamp including a transformer ( | 02-02-2012 |
Naveen Yadlapalli, Billerica, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20110062878 | BALLAST WITH LAMP FILAMENT DETECTION - A ballast ( | 03-17-2011 |
| 20110062879 | BALLAST WITH LAMP-DIAGNOSTIC FILAMENT HEATING, AND METHOD THEREFOR - A ballast ( | 03-17-2011 |
Naveen Yajaman, Bellevue, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20080294883 | Mock exceptions in a host add-in environment - Mock exceptions, including mock exception types, are defined by a host to be raised in a plug-in. The mock exceptions might be sanitized. They might be transported from the plug-in to the host. Mock exceptions might also be mapped to real exceptions, which are raised in the host and handled by the host. | 11-27-2008 |
Naveen Zalpuri, Foster City, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090158047 | HIGH PERFORMANCE SECURE CACHING IN THE MID-TIER - In a multi-tier data server system, data from the first tier is cached in a mid-tier cache of the middle tier. Access control information from the first tier for the data is also cached within the mid-tier cache. Caching the security information in the middle tier allows the middle tier to make access control decisions regarding requests for data made by clients in the outer tier. | 06-18-2009 |
| 20120005433 | RESPONSE HEADER INVALIDATION - Systems, methods, and other embodiments associated with content invalidation are described. One example method includes providing an invalidation directive in a header of a response. | 01-05-2012 |