Natsuo

Natsuo Aiika, Hyogo JP

Patent application number	Description	Published
20090161439	Nonvolatile Semiconductor Memory Device - According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.	06-25-2009

Patent application number	Description	Published
20100140711	SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Generation of dislocation and increase of diffusion resistance at edge portions of source/drain regions in a CMIS are prevented. When source/drain regions in a CMIS are formed, argon is implanted to a P-well layer as a dislocation-suppressing element and nitrogen is implanted to an N-well layer as a dislocation-suppressing element before an ion implantation of impurities to a silicon substrate. In this manner, by separately implanting dislocation-suppressing elements suitable for each of the P-well layer and the N-well layer as well as suppressing the generation of dislocation, increase of diffusion resistance can be suppressed, yield can be improved, and the reliability of devices can be increased.	06-10-2010

Patent application number	Description	Published
20090134467	SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG.	05-28-2009