Patent application number | Description | Published |
20080231352 | Adjusting PLL/analog supply to track CPU core supply through a voltage regulator - A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core. | 09-25-2008 |
20090079406 | High-voltage tolerant low-dropout dual-path voltage regulator with optimized regulator resistance and supply rejection - A voltage regulator includes an amplifier having first and second outputs, a feedback path coupled between a first input and the first output of the amplifier, and a feed-forward path between the second output of the amplifier and a switch coupled to a reference potential. In operation, a first control signal from the second output of the amplifier is generated based on a comparison of a reference signal and a feedback signal into the first input of the amplifier. The first control signal controls the switch to maintain a substantially constant supply voltage. A second control signal is generated along the feedback path to control controls the amount of supply voltage. | 03-26-2009 |
20090243659 | METHOD AND DEVICE FOR DETECTING THE ABSENCE OF A PERIODIC SIGNAL - A method and device may determine the absence of a periodic signal or the absence of an edge of the periodic signal. The periodic signal may be a transmitted clock signal in a forwarded clock architecture. The periodic signal may be delayed by a fixed phase difference to produce a delayed periodic signal. The phase difference between the periodic signal and the delayed periodic signal may be determined. If the determined phase difference is above or below the fixed phase difference by a predetermined amount or more the periodic signal may be missing an edge. If the absence of the periodic signal or the absence of the edge of the periodic signal is detected, an error signal may be asserted. The error signal may be an in-band reset signal. | 10-01-2009 |
20100327936 | METHOD AND APPARATUS FOR DETERMINING WITHIN-DIE AND ACROSS-DIE VARIATION OF ANALOG CIRCUITS - Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property. | 12-30-2010 |
20110285469 | METHOD AND APPARATUS FOR DETERMINING WITHIN-DIE AND ACROSS-DIE VARIATION OF ANALOG CIRCUITS - Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property. | 11-24-2011 |
20110298501 | Methods and Apparatuses for Delay-Locked Loops and Phase-Locked Loops - A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation. | 12-08-2011 |
20120019285 | METHOD AND APPARATUS FOR FAST WAKE-UP OF ANALOG BIASES - Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal. | 01-26-2012 |
20130086410 | FREQUENCY SYNTHESIS METHODS AND SYSTEMS - Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority. | 04-04-2013 |
20130300475 | LOW POWER, JITTER AND LATENCY CLOCKING WITH COMMON REFERENCE CLOCK SIGNALS FOR ON-PACKAGE INPUT/OUTPUT INTERFACES - Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components. | 11-14-2013 |
20130307631 | APPARATUS AND SYSTEM FOR DIGITALLY CONTROLLED OSCILLATOR - Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply. | 11-21-2013 |
20140103973 | SYSTEM AND METHOD FOR SCALING POWER OF A PHASE-LOCKED LOOP ARCHITECTURE - Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system. | 04-17-2014 |
20140254734 | APPARATUS FOR DYNAMICALLY ADAPTING A CLOCK GENERATOR WITH RESPECT TO CHANGES IN POWER SUPPLY - Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word. | 09-11-2014 |