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Narendra B.

Narendra B. Dahotre, Knoxville, TN US

Patent application number	Description	Published
20090035723	MATERIAL WITH A REPETITIVE PATTERN OF MICRO-FEATURES FOR APPLICATION IN A LIVING ORGANISM AND METHOD OF FABRICATION - A material configured for implantation in a living organism. In some embodiments, the material includes a mechanical surface that has long range ordered micro-features. A repetitive pattern of hierarchical micro-features is incorporated in some embodiments, and in some embodiments the micro-features are composite in nature, and may include nano-structures. One embodiment provides a method of modifying the surface of a tissue in a living organism. The method includes a step of dividing a laser beam into a plurality of laser beams and a further step of guiding the plurality of laser beams to create an interference pattern at the surface of the material, and a repetitive pattern of micro-features is formed on the surface of the tissue.	02-05-2009
20110183292	MATERIAL WITH A REPETITIVE PATTERN OF MICRO-FEATURES FOR APPLICATION IN A LIVING ORGANISM AND METHOD OF FABRICATION - An assembly configured for implantation in a living organism is provided. In some embodiments, the material includes a mechanical surface that has long range ordered micro-features. A repetitive pattern of hierarchical micro-features is incorporated in some embodiments, and in some embodiments the micro-features are composite in nature, and may include nano-structures. In one embodiment an assembly has a first article has a mechanical surface configured to be disposed in contact with a material that is not live biological tissue and a second article comprising a bio-interfacial surface configured to be disposed in contact with live biological tissue. Some embodiments include a screw or a post.	07-28-2011

Narendra B. Devta-Prasa, Milpitas, CA US

Patent application number	Description	Published
20100162060	DFT TECHNIQUE TO APPLY A VARIABLE SCAN CLOCK INCLUDING A SCAN CLOCK MODIFIER ON AN IC - A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic configured to provide a scan clock signal based on the at least one selected clock signal and at least one other clock control signal received from the test equipment, wherein the first and the at least one other clock control signals are different clock control signals.	06-24-2010

Narendra B. Devta-Prasanna, Milpitas, CA US

Patent application number	Description	Published
20100153795	METHOD FOR GENERATING TEST PATTERNS FOR SMALL DELAY DEFECTS - A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.	06-17-2010
20100262394	METHOD AND AN APPARATUS FOR EVALUATING SMALL DELAY DEFECT COVERAGE OF A TEST PATTERN SET ON AN IC - A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.	10-14-2010
20100262876	TEST CIRCUIT AND METHOD FOR TESTING OF INFANT MORTALITY RELATED DEFECTS - The disclosure provides embodiments of ICs and a method of testing an IC. In one embodiment, an IC includes: (1) a functional logic path having a node and at least one sequential logic element and (2) test circuitry coupled to the functional logic path and having a delay block, the test circuitry configured to form a testable path including the delay block and the node in response to a test mode signal, wherein a delay value of the delay block is selected to detect a small delay defect associated with the node.	10-14-2010

Narendra B. Devta-Prasanna, San Jose, CA US

Patent application number	Description	Published
20120072797	DESIGN-FOR-TEST TECHNIQUE TO REDUCE TEST VOLUME INCLUDING A CLOCK GATE CONTROLLER - Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.	03-22-2012