Patent application number | Description | Published |
20100109683 | SEMICONDUCTOR DEVICE - A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element. | 05-06-2010 |
20110084722 | Semiconductor device and test method thereof - A semiconductor device includes a plurality of memory chips arranged in a layered manner, each including a substrate and a memory cell array, and a plurality of current paths provided while penetrating through the memory chips. Each of the memory chips includes a test circuit that reads test data from a corresponding one of the memory cell array and outputs a layer test result signal responding to the test data to a different current path for each of the memory chips. | 04-14-2011 |
20110084744 | Semiconductor device, adjustment method thereof and data processing system - Read data that are output from core chips are accurately captured into an interface chip. Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that adjusts the period of time required from the reception of the read command to the outputting of the read data from the data output circuit. The interface chip includes a data input circuit that captures read data, and an input timing adjustment circuit that adjusts the timing for the data input circuit to allow the capturing of the read data after issuing the read command. In this manner, a sufficient latch margin for read data on the interface chip side can be secured. | 04-14-2011 |
20110085403 | Semiconductor memory device and information processing system including the same - The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. A bit number of external unit data that is simultaneously input and output between an external device and the interface chip changes in the interface chip, and the interface chip changes chip selection information for comparison with the chip identification information, according to the bit number of the external unit data. As a result, the page configuration does not need to be changed, when the I/O configuration is changed. | 04-14-2011 |
20110087811 | Semiconductor device, control method for the semiconductor device and information processing system including the same - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 04-14-2011 |
20110093735 | Semiconductor memory device, method of adjusting the same and information processing system including the same - Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side. | 04-21-2011 |
20120092943 | Semiconductor device and test method thereof - plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal. | 04-19-2012 |
20120127812 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a plurality of first data signals in response to data stored in selected ones of the first memory cells, a plurality of first data electrodes, and a first data control circuit coupled to the first control logic circuit and the first data electrodes. A second semiconductor chip includes a second memory cell array including a plurality of second memory cells, a second control logic circuit accessing the second memory cell array and producing a plurality of second data signals in response to data stored in selected ones of the second memory cells. The second control logic circuit is configured to store second timing adjustment information and to produce a second output timing signal. | 05-24-2012 |
20130010515 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips. | 01-10-2013 |
20130275798 | SEMICONDUCTOR DEVICE, CONTROL METHOD FOR THE SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 10-17-2013 |
20140016388 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A system includes a first device, a second device, and a bus interconnecting the first and second devices to each other, wherein the first device includes a first semiconductor chip that includes a first memory cell array including a plurality of first memory cells, a first control logic circuit accessing the first memory cell array and producing a first data signal in response to data stored in a selected one of the first memory cells, the first control logic circuit being configured to store first timing adjustment information and to produce a first output timing signal that is adjustable in timing of change from an inactive level to an active level by the first timing adjustment information, a first data electrode, and a first data control circuit coupled to the first control logic circuit and the first data electrode. | 01-16-2014 |
20140056086 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF ADJUSTING THE SAME AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells. | 02-27-2014 |
20140078843 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data. | 03-20-2014 |
20140089723 | SEMICONDUCTOR DEVICE, CONTROL METHOD FOR THE SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 03-27-2014 |
20140140160 | Semiconductor Device - A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element | 05-22-2014 |
20140165018 | SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM - A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay. | 06-12-2014 |
20140369145 | Semiconductor Device and Test Method Thereof - A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data. | 12-18-2014 |