Patent application number | Description | Published |
20080251930 | SEMICONDUCTOR DEVICE AND DUMMY PATTERN ARRANGEMENT METHOD - A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern. | 10-16-2008 |
20080309374 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 12-18-2008 |
20090019413 | System and method for automatic layout of integrated circuit - An automatic layout apparatus is provided with: a storage device storing a cell library containing therein cell library data; and a layout tool obtaining from the cell library the cell library data associated with cells to be placed as described in a netlist to perform automatic placement of the cells to be placed. The obtained cell library data include layout coordinates of diffusion layers within the cells to be placed. The layout tool determines positions of the cells to be placed, referring to the layout coordinates of the diffusion layers. | 01-15-2009 |
20090049420 | Dummy pattern placement apparatus, method and program and semiconductor device - The load of OPC processing (especially, the load of bias processing) has been increasing due to optical effects involved in the placement of a dummy pattern. A pattern placement apparatus places dummy patterns in a layout region where a plurality of wiring patterns is placed. The pattern placement apparatus comprises: a placement region setting section that sets a placement region, where each of the dummy patterns should be placed, in an intermediate region between the adjacent wiring patterns at substantially constant intervals to the adjacent writing patterns; and a pattern placement section that places the dummy pattern in the placement region. | 02-19-2009 |
20090093099 | Layout method and layout apparatus for semiconductor integrated circuit - In a layout method for a semiconductor integrated circuit by using cell library data, a plurality of cell patterns are arranged in a first direction. One of gate patterns in one of the plurality of cell patterns is specified as a reference gate pattern. An additional cell pattern is arranged in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area containing the reference gate pattern satisfies a constraint condition. | 04-09-2009 |
20100001763 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 01-07-2010 |
20100077371 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 03-25-2010 |
20100084769 | SEMICONDUCTOR DEVICE AND DUMMY PATTERN ARRANGEMENT METHOD - A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction different from the first direction, wherein each of the plurality of dummy patterns is arranged spaced apart from each of the plurality of wiring patterns and includes one or more dummy lands formed by separating a part of the dummy pattern opposed to the wiring pattern, from the rest part of the dummy pattern. | 04-08-2010 |
20110055776 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE - This is a method of designing a semiconductor device. The method includes: arranging cells used for an electric circuit and wirings respectively connected to gates of the cells in a coordinate region to create chip layout data including the cells, gates and wirings; checking whether each gate included in the chip layout data is in antenna violation; storing antenna violation information in an error-remaining portion library, the antenna violation information representing an antenna violation gate group, in which gates in the antenna violation are contained, in the gates included in the chip layout data; performing lithography simulation for the chip layout data to create predicted layout data after photoresist exposure; selecting the antenna violation gate group from the gates included in the predicted layout data, with reference to the error-remaining library; calculating a calculated value representing a ratio of an area of an wiring of the wirings with respect to an area of a gate of the antenna violation gate group connected to the wiring, for each gate of the antenna violation group; and adjusting a size of the gate of the antenna violation gate group, when the calculated value of the antenna violation group included in the predicted layout data is in a range between a first and second setting value. | 03-03-2011 |
20110265056 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A layout design method of a semiconductor integrated circuit includes providing a cell layout including a cell that includes a gate or a plurality of gates extending in a first direction, a plurality of diffusion layers, a first boundary of the cell in parallel with the gate or the plurality of gates, a second boundary of the cell being in an opposite side of the first boundary of the cell, a first distance, a second distance, A third distance, and a fourth distance, regenerating the cell layout to set the first distance and the second distance to a first value, or to set the third distance and the fourth distance to a second value, and generating a library data of the cell for a placement and routing tool, based on the cell layout. | 10-27-2011 |
20110289467 | Layout method and layout apparatus for semiconductor integrated circuit - A layout method of a semiconductor integrated circuit by using cell library data includes specifying a gate in a predetermined cell as a reference gate, and automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from the reference gate meets a preset gate data density condition. | 11-24-2011 |