Patent application number | Description | Published |
20100327250 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor. | 12-30-2010 |
20110266516 | PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device includes a plurality of word lines, a plurality of bit lines disposed to be crossed with the plurality of word lines, switching devices disposed at intersections of the plurality of word lines and the plurality of bit lines, heating electrodes connected to the switching devices respectively, heat absorbing layers disposed between adjacent heating electrodes, and phase change layers formed on the heating electrodes and the heat absorbing layers and extended in the same direction of the bit line. | 11-03-2011 |
20120156840 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor. | 06-21-2012 |
20130334488 | VERTICAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical memory device capable of minimizing a cell size and improving current drivability and a method of fabricating the same are provided. The vertical memory device includes a common source region and source regions formed on the common source region and extending in a first direction. Channel regions are formed on each of the source regions, the channel regions extending in the first direction. Trenches are formed between the channel regions. A drain region is formed on each of the channel regions. A conductive layer is formed its on a side of each of the channel regions, the conductive layer extending to the first direction. A data storage material is formed on each of the drain regions. | 12-19-2013 |
20140054538 | 3-DIMENSIONAL STACK MEMORY DEVICE - A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type. | 02-27-2014 |
20140113427 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers. | 04-24-2014 |
20140117304 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device includes a plurality of column selection switches, a plurality of variable resistance memory cells configured to be stacked and selected by the plurality of column selection switches, and a bit line connected to the plurality of variable resistance memory cells. Each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines arranged to be stacked and a variable resistor connected in parallel to the OTS element. | 05-01-2014 |
20140160839 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 06-12-2014 |
20140162429 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 06-12-2014 |
20140166971 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor. | 06-19-2014 |
20140167030 | VERTICAL TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region. | 06-19-2014 |
20140239247 | TRANSISTOR, RESISTANCE VARIABLE MEMORY DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first to work function. | 08-28-2014 |
20140248750 | VERTICAL TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region. | 09-04-2014 |
20140268996 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround the pillar-shaped gate electrode. A variable resistance layer formed in an outer portion of the current transfer layer. A blocking layer blocks a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and diverts the current flowing through the current transfer layer to the variable resistance layer. | 09-18-2014 |
20140299831 | 3D VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D variable resistance memory device and a method of manufacturing the same are provided. A semiconductor substrate includes a peripheral area, having a top surface, wherein a peripheral circuit is formed in the peripheral area. The peripheral circuit includes a driving transistor formed on a surface of the semiconductor substrate, wherein the semiconductor substrate forms the channel of the driving transistor. The semiconductor substrate includes a cell area, having a top surface, wherein a height of the top surface of the cell area is lower than a height of the top surface of the peripheral area, thereby defining a trench in the cell area. A plurality of memory cells, each include a switching transistor formed on the semiconductor substrate in the cell area, a channel extending in a direction substantially perpendicular to a surface of the semiconductor substrate, and a variable resistance layer that selectively stores data in response to the switching transistor. | 10-09-2014 |
20140301128 | 3D VARIABLE RESISTANCE MEMORY DEVICE HAVING JUNCTION FET AND DRIVING METHOD THEREOF - A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer. | 10-09-2014 |
20140321193 | 3D VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer. | 10-30-2014 |
20150048292 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, a resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device includes a pillar extending substantially perpendicular from a semiconductor substrate, the pillar including an inner portion and an outer portion surrounding the inner portion. A junction region is formed in an upper region and a lower region of the vertical pillar, and a gate surrounds the pillar. The inner portion of the pillar includes a semiconductor layer having a lattice constant that is larger than a lattice constant of the outer portion of the pillar. | 02-19-2015 |
20150048293 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The 3D semiconductor device includes a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the LDD region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain. | 02-19-2015 |
20150048294 | VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. The inner portion of the vertical pillar has a lattice constant smaller than that of the outer portion of the vertical pillar. | 02-19-2015 |
20150048295 | SEMICONDUCTOR DEVICE HAVING FIN GATE, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device includes an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region, and a fin gate extending to overlap an upper surface and a lateral surface of the active pillar. The first region of the active pillar is formed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar. | 02-19-2015 |
20150048296 | SEMICONDUCTOR DEVICE HAVING FIN GATE, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant. | 02-19-2015 |