Patent application number | Description | Published |
20090085206 | METHOD OF FORMING SOLDER BUMPS ON SUBSTRATES - A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps. | 04-02-2009 |
20090166396 | MICROBALL ATTACHMENT USING SELF-ASSEMBLY FOR SUBSTRATE BUMPING - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a plurality of bonding pads thereon, and providing a plurality of solder microballs, the microballs including a coating thereon. The method also includes flowing the solder microballs onto the substrate and positioning the solder microballs on the bonding pads. The method also includes heating the solder microballs to reflow and form a joint between the solder microballs and the bonding pads. Other embodiments are described and claimed. | 07-02-2009 |
20090238233 | OPTICAL DIE STRUCTURES AND ASSOCIATED PACKAGE SUBSTRATES - Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers. | 09-24-2009 |
20090238516 | SUBSTRATES FOR OPTICAL DIE STRUCTURES - Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard. | 09-24-2009 |
20090242109 | MECHANICAL ADHESION OF COPPER METALLIZATION TO DIELECTRIC WITH PARTIALLY CURED EPOXY FILLERS - In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed. | 10-01-2009 |
20090277866 | Method of enabling solder deposition on a substrate and electronic package formed thereby - An electronic package includes a substrate ( | 11-12-2009 |
20100044862 | METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR SUBSTRATE - A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate. | 02-25-2010 |
Patent application number | Description | Published |
20080241547 | METHODS OF LASER SURFACE MODIFICATION OF CERAMIC PACKAGES FOR UNDERFILL SPREAD CONTROL AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include heating a portion of a ceramic substrate adjacent to a C | 10-02-2008 |
20090061232 | Methods of laser surface modification of ceramic packages for underfill spread control and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include heating a portion of a ceramic substrate adjacent to a C | 03-05-2009 |
20090084155 | Method to Form Pin Having Void Reducing Pin Head and Flattening Head to Perform the Method - A method of forming a pin adapted to be used in a PGA joint, and a flattening head used to perform the method. The method includes: providing a pin blank; and forming a pin head by coining an end of the pin blank using a flattening head thereby forming the pin, the pin having a pin stem and the pin head attached to the pin stem, the flattening head being shaped to impart a topography to an underside surface to the pin head that is non-smooth during coining, the topography being adapted to allow gases to escape from a pin-attach solder disposed adjacent to the underside surface. | 04-02-2009 |
20100276185 | BARRIER LAYER FOR FINE-PITCH MASK-BASED SUBSTRATE BUMPING - A structure that may be used in substrate solder bumping comprises a substrate ( | 11-04-2010 |
20110108999 | Microelectronic package and method of manufacturing same - A microelectronic package comprises a die ( | 05-12-2011 |
20110215464 | Semiconductor package with embedded die and its methods of fabrication - Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs. | 09-08-2011 |
20110241186 | FORMING METAL FILLED DIE BACK-SIDE FILM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate. | 10-06-2011 |
20110241195 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure. | 10-06-2011 |
20110254124 | FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material. | 10-20-2011 |
20120074580 | METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C | 03-29-2012 |
20130023088 | METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands. | 01-24-2013 |
20140367843 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure. | 12-18-2014 |