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Nakasaki
Kiyohiko Nakasaki, Shizuoka JP
| Patent application number | Description | Published |
|---|---|---|
| 20080248058 | Plant Disease Control Agent And Method For Controlling Plant Disease - The present invention provides a plant disease control agent which is stable and safe in terms of leaving no residue and a method for controlling plant diseases using the same. The plant disease control agent comprises a fragment of an inky cap mushroom, and plant diseases are controlled by using the plant disease control agent. The plant disease control agent may be a suspension comprising the fragment of the inky cap mushroom or a solid material composed of the suspension and a carrier to which the suspension is absorbed. The inky cap mushroom is preferably | 10-09-2008 |
Kiyohiko Nakasaki, Yokohoma-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100212384 | Method for Producing Functional Compost, Functional Compost and Compost for Proliferation of Filamentous Fungus - The method for producing functional compost according to the invention includes: inoculating a filamentous fungus with a function, such as the | 08-26-2010 |
Kiyohiko Nakasaki, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110177519 | Method for Detecting Functional Mold, Method for Evaluating Functional Mold-Containing Product and Primer Pair - The present invention provides a method of detecting a functional filamentous fungus, wherein the functional filamentous fungus, | 07-21-2011 |
Ryusuke Nakasaki, Chiyoda-Ku JP
| Patent application number | Description | Published |
|---|---|---|
| 20120180725 | CVD APPARATUS - A cold wall type CVD apparatus that can enhance a raw material yield is provided. The CVD apparatus has a raw material gas jetting unit | 07-19-2012 |
Toshio Nakasaki, Kyoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20120091555 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate. | 04-19-2012 |
Yasushi Nakasaki, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090242958 | NAND-TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide, | 10-01-2009 |
| 20110266612 | NAND-TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide, | 11-03-2011 |
| 20120091420 | NONVOLATILE RESISTANCE CHANGE DEVICE - According to one embodiment a first variable resistance layer which is arranged between a second electrode and a first electrode and in which a first conductive filament is capable of growing based on metal supplied from the second electrode, and an n-th variable resistance layer which is arranged between an n-th electrode and an (n+1)-th electrode and in which an n-th conductive filament whose growth rate is different from the first conductive filament is capable of growing based on metal supplied from the (n+1)-th electrode are included, a configuration in which a plurality of conductive filaments is electrically connected in series between the first electrode layer and the (n+1)-th electrode layer is included, and a resistance is changed in a stepwise manner. | 04-19-2012 |
Yasushi Nakasaki, Kanagawa-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20080305647 | Method for Manufacturing a Semiconductor Device - It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower. | 12-11-2008 |
| 20110241101 | SEMICONDUCTOR MEMORY ELEMENT AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge accumulation film provided on the tunnel insulator having a film thickness of 0.9 nm or more and 2.8 nm or less and the charge accumulation film containing cubic HfO | 10-06-2011 |
