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Na, US
Chen Na, Katy, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090172062 | EFFICIENT FIXED-POINT IMPLEMENTATION OF AN FFT - A fast Fourier transform (FFT) is performed on first-fourth input data points. Real and imaginary portions of the first input data point are stored in first and second registers. Real and imaginary portions of the second input data point are stored in third and fourth registers. Real and imaginary portions of the third input data point are stored in fifth and sixth registers. Real and imaginary portions of the fourth input data point are stored in seventh and eighth registers. Operations are performed in place in the first-eight registers and in a ninth register to generate a first-fourth output data points stored in the registers that represent an FFT of the first-fourth input data points. The radix-4 FFT may be cascaded to perform higher bit-level FFTs on sets of data points. Furthermore, the data points may be reordered between cascaded radix-4 FFTs to enable efficient use of memory. | 07-02-2009 |
Hanjoo Na, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110215654 | Switchable Capacitor Arrays for Preventing Power Interruptions and Extending Backup Power Life - A technique for preventing power interruptions and extending backup power life is provided. The technique automatically prevents power interruptions in a line between a power source and a load. The technique can also extend the operating life of the power source. In one embodiment, a circuit for preventing power interruptions is provided. The circuit may include at least one arrays of capacitors, with the capacitors being arranged in parallel within an array, at least one switching elements configured to couple the at least one array of capacitors to a load, and a controller operatively coupled to the at least one switching element. The controller is configured to selectively drive the at least one switching element based on predetermined criteria. | 09-08-2011 |
Henry Cheng Na, Cincinnati, OH US
| Patent application number | Description | Published |
|---|---|---|
| 20090288765 | Methods for the Manufacture of Fastener Tabs - A method of making fastener tabs includes providing a length of tab substrate. A first adhesive is applied to a first adhesive region of the length of tab substrate. A second adhesive is applied to a second adhesive region of the length of tab substrate. The first and second adhesive regions are adjacent such that the first and second adhesive regions have a common longitudinal edge. The first and second adhesive regions have different adhesion characteristics. | 11-26-2009 |
| 20090292270 | Fastener Tab - A fastener tab includes a tab substrate having a first side and a second side. A first adhesive region is applied to an installation portion of the first side and a second adhesive region is applied to a fastening portion of the first side. The first and second adhesive regions are configured to provide different adhesion characteristics. A disposable absorbent article includes at least one fastener tab and may also include release and attachment substrates that releasably retain the second adhesive region for storage and use, respectively. | 11-26-2009 |
Jeong Seok Na, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120115325 | ION-INDUCED ATOMIC LAYER DEPOSITION OF TANTALUM - Systems, methods, and apparatus for depositing a tantalum layer on a wafer substrate are disclosed. In one aspect, a tantalum layer may be deposited on a surface of a wafer substrate using an ion-induced atomic layer deposition process with a tantalum precursor. A copper layer may be deposited on the tantalum layer. | 05-10-2012 |
John Kuk Na, State College, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20110191894 | METHODS AND COMPOSITIONS RELATING TO CONROLLED INDUCTION OF PLANT SENESCENCE - Methods and compositions for promoting senescence in plants are provided. Methods and compositions for promoting senescence in plants by increased expression of an exogenous or endogenous abscisic-acid-activated protein kinase-interacting protein, AKIP. In specific embodiments, transgenic plants are provided expressing increased abscisic-acid-activated protein kinase-interacting protein, AKIP, during the developmental stage of senescence, thereby promoting enhanced plant senescence. | 08-04-2011 |
Jong-Hon Theodore Na, Irvine, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120002731 | METHOD AND SYSTEM FOR FAST DIGITAL CHANNEL CHANGE UTILIZING TIME-STAMP MANAGEMENT - A video stream demultiplxer receives video streams comprising a selected current content channel and one or more adjacent content channels. Time stamp management is concurrently performed on the adjacent content channels while decoding the selected current content channel. Timing information such as Decoding Time Stamp (DTS) and Presentation Time Stamp (PTS) values, and/or random access points (RAPs) may be determined for pictures stored for the selected current content channel and the adjacent content channels. The determined timing information is utilized to determine a Program Clock Reference (PCR) value for each of the selected current channel and the adjacent channels for channel monitoring. A timebase, derived from a PCR rate that is determined based on the determined PCR value, is determined for decoding the selected current content channel. An adjacent content channel, which is primed during decoding of the selected current content channel, may be directly decoded for display if selected. | 01-05-2012 |
Kun Na, Salt Lake City, UT US
| Patent application number | Description | Published |
|---|---|---|
| 20090274753 | PH-SENSITIVE POLYMERIC MICELLES FOR DRUG DELIVERY - Mixed micelles containing poly(L-histidine)-poly(ethylene glycol) block copolymer and poly(L-lactic acid)-poly(ethylene glycol) block copolymer are a pH-sensitive drug carrier that release the drug in an acidic microenvironment, but not in the blood. Since the microenvironment of solid tumors is acidic, these mixed micelles are useful for treating cancer, including those cancers exhibiting multidrug resistance. Targeting ligands, such as folate, can also be attached to the mixed micelles for enhancing drug delivery into cells. Methods of treating a warm-blooded animal with such a drug are disclosed. | 11-05-2009 |
Min Gyu Na US
| Patent application number | Description | Published |
|---|---|---|
| 20120113673 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device a light transmissive substrate, a light emitting structure disposed on the light transmissive substrate, comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a conductive layer disposed on the second conductive type semiconductor layer, a first electrode part disposed on the conductive layer, with at least predetermined region in contact with the first conductive type semiconductor layer, passing through the conductive layer, the second conductive type semiconductor layer and the active, and a first insulation layer disposed between the conductive layer and the first electrode part, between the second conductive type semiconductor layer and the first electrode part and between the active layer and the first electrode part. | 05-10-2012 |
Myung-Hee Na, Lagrangeville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100276753 | Threshold Voltage Adjustment Through Gate Dielectric Stack Modification - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 11-04-2010 |
| 20120108017 | THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION - Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration. | 05-03-2012 |
Nanju Na, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090085155 | METHOD AND APPARATUS FOR PACKAGE-TO-BOARD IMPEDANCE MATCHING FOR HIGH SPEED INTEGRATED CIRCUITS - A method of package-to-board impedance matching for high speed integrated circuits (ICs). Multiple solder balls are attached to an IC package. The IC package includes multiple conductive interconnect layers, where one of the conductive interconnect layers is coupled to one or more of the multiple solder balls. Multiple vias are coupled between different conductive interconnect layers. An inductive element is coupled between an interconnect lead and a via land in the conductive interconnect layer within the IC package. The physical layout dimensions of the inductive element are configured such that the inductive element provides an inductance value that is sufficient to offset a parasitic capacitance provided by the conductive interconnect layers and the solder balls. The inductive element may be a bond wire, an inductive interconnect, or a spiral interconnect. | 04-02-2009 |
| 20100073893 | MINIMIZING PLATING STUB REFLECTIONS IN A CHIP PACKAGE USING CAPACITANCE - Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer. | 03-25-2010 |
| 20110061898 | REDUCING CROSS-TALK IN HIGH SPEED CERAMIC PACKAGES USING SELECTIVELY-WIDENED MESH - One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package. | 03-17-2011 |
| 20110103030 | Packages and Methods for Mitigating Plating Stub Effects - Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground. | 05-05-2011 |
| 20110133326 | Reducing Plating Stub Reflections in a Chip Package Using Resistive Coupling - Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer. | 06-09-2011 |
Nanju Na, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100099219 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS - Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations. | 04-22-2010 |
| 20120032330 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS - Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations. | 02-09-2012 |
Onegyun Na, Boise, ID US
| Patent application number | Description | Published |
|---|---|---|
| 20100134146 | VOLTAGE LEVEL TRANSLATOR AND METHOD - A level translator includes an NMOS input transistor and a PMOS input transistor having respective gates receiving an input voltage. The input transistors compare the input voltage to respective first and second supply voltages. The input voltage is also applied to an inverter that is powered by the first and second supply voltages. An output terminal is coupled to a third supply voltage through a PMOS output transistor and to a fourth supply voltage through an NMOS output transistor. The third and fourth supply voltages are outside of a range bounded by the first and second supply voltages. The respective drains of the input transistors and the output of the inverter are coupled to the gates of the output transistors in a manner that either turns the PMOS output transistor ON and the NMOS output transistor OFF or turns the NMOS output transistor ON and the PMOS output transistor OFF. | 06-03-2010 |
| 20110235450 | CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD - Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance. | 09-29-2011 |
| 20110310687 | CURRENT SENSE AMPLIFIERS, MEMORY DEVICES AND METHODS - A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals. | 12-22-2011 |
Qiyuan Na, Charlotte, NC US
| Patent application number | Description | Published |
|---|---|---|
| 20090144546 | APPLICATION CONTROLLED ENCRYPTION OF WEB BROWSER DATA - A browser cache-securing component facilitates online communication of confidential data, such as for financial information, purchasing transactions, or user identification. Caching webpages for subsequent presentation enhances user productivity and efficiency while reducing burdens on network resources. Yet, the security risks of intrusions into cache memory are mitigated by retaining encrypted data in cache memory without prior decryption. A modest overhead in decrypting when and if the webpage is to be presented again gains a security and privacy advantage without taking away functionality. Decrypted versions of confidential data can thereby be relegated to volatile memory. Upon termination of a session, a session key shared by a network server is deleted, preventing subsequent decryption. Executing the browser cache-securing component in a virtual machine environment allows multiple browser types to benefit from the security feature. | 06-04-2009 |
| 20110238992 | APPLICATION CONTROLLED ENCRYPTION OF WEB BROWSER CACHED DATA - A browser cache-securing component facilitates online communication of confidential data, such as for financial information, purchasing transactions, or user identification. Caching webpages for subsequent presentation enhances user productivity and efficiency while reducing burdens on network resources. Yet, the security risks of intrusions into cache memory are mitigated by retaining encrypted data in cache memory without prior decryption. A modest overhead in decrypting when and if the webpage is to be presented again gains a security and privacy advantage without taking away functionality. Decrypted versions of confidential data can thereby be relegated to volatile memory. Upon termination of a session, a session key shared by a network server is deleted, preventing subsequent decryption. Executing the browser cache-securing component in a virtual machine environment allows multiple browser types to benefit from the security feature. | 09-29-2011 |
Shuo Na, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080283799 | NANOWIRES-BASED TRANSPARENT CONDUCTORS - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates. | 11-20-2008 |
| 20080286447 | NANOWIRES-BASED TRANSPARENT CONDUCTORS - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates. | 11-20-2008 |
| 20100243295 | NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like. | 09-30-2010 |
| 20110088770 | NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like. | 04-21-2011 |
| 20110285019 | TRANSPARENT CONDUCTORS COMPRISING METAL NANOWIRES - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates. | 11-24-2011 |
| 20110297642 | NANOWIRE-BASED TRANSPARENT CONDUCTORS AND APPLICATIONS THEREOF - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like. | 12-08-2011 |
Young-Hye Na, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100294740 | Directed self-assembly of block copolymers using segmented prepatterns - An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls. | 11-25-2010 |
| 20100297847 | Method of forming sub-lithographic features using directed self-assembly of polymers - Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes. | 11-25-2010 |
| 20110120940 | POLYMERIC FILMS MADE FROM POLYHEDRAL OLIGOMERIC SILSESQUIOXANE (POSS) AND A HYDROPHILIC COMONOMER - A composite membrane includes a filtration membrane and a layer on a surface of the filtration membrane. The layer includes a polymer including a polyhedral oligomeric silsesquioxane (POSS) derivative with a hydrophilic moiety attached to at least one vertex thereof. A method for making a composite membrane includes applying to a surface of a filtration membrane a photopolymerizable composition including a POSS compound, a hydrophilic comonomer, and a photoinitiator. The composition is cured to form a hydrophilic layer on the filtration membrane. | 05-26-2011 |
| 20110120941 | COMPOSITE MEMBRANES WITH PERFORMANCE ENHANCING LAYERS - A composite membrane includes a filtration membrane with a surface; and a layer on the surface of the filtration membrane. The layer includes a polymer including a poly(ethylene glycol) moiety cross-linked with an ammonium salt or a precursor of an ammonium salt | 05-26-2011 |
| 20110147983 | METHODS OF DIRECTED SELF-ASSEMBLY AND LAYERED STRUCTURES FORMED THEREFROM - A method of forming a layered structure comprising a domain pattern of a self-assembled material comprises: disposing on a substrate a photoresist layer comprising a non-crosslinking photoresist; optionally baking the photoresist layer; pattern-wise exposing the photoresist layer to first radiation; optionally baking the exposed photoresist layer; and developing the exposed photoresist layer with a non-alkaline developer to form a negative-tone patterned photoresist layer comprising non-crosslinked developed photoresist; wherein the developed photoresist is not soluble in a given organic solvent suitable for casting a given material capable of self-assembly, and the developed photoresist is soluble in an aqueous alkaline developer and/or a second organic solvent. A solution comprising the given material capable of self-assembly dissolved in the given organic solvent is casted on the patterned photoresist layer, and the given organic solvent is removed. The casted given material is allowed to self-assemble while optionally heating and/or annealing the casted given material, thereby forming the layered structure comprising the domain pattern of the self-assembled given material. | 06-23-2011 |
| 20110209106 | METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY - A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate. | 08-25-2011 |
| 20120012527 | COMPOSITE MEMBRANE WITH MULTI-LAYERED ACTIVE LAYER - A polymeric membrane includes an active layer on a support. The active layer includes at least two chemically distinct crosslinked, polyamide films, and the films are crosslinked with each other at an interface. | 01-19-2012 |
Yun-Chung Na, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100258746 | Massive parallel generation of nonclassical photons via polaritonic superfluid to mott- insulator quantum phase transition - Deterministic generation of nonclassical photons by producing a dilute gas of exciton-polaritons in a solid-state microcavity that includes a periodic array of potential well traps. A photon-exciton frequency detuning is modulated in the microcavity to produce a polaritonic quantum phase transition from a superfluid state to a Mott-insulator state. The nonclassical photons are then generated simultaneously by radiative decay of exciton-polaritons in the microcavity. The nonclassical photons may be indistinguishable single photons, in which case the dilute gas of exciton-polaritons is produced such that on to average there is one polariton per potential well trap. Alternatively, the generated nonclassical photons may be polarization-entangled photon pairs, in which case the dilute gas of exciton-polaritons is produced such that on average there are two polaritons per potential well trap. | 10-14-2010 |
| 20110235968 | MULTIMODE OPTICAL COUPLER INTERFACES - Optical interfaces that may be employed between large-core optical fibers and chip-scale optoelectronic devices. Described herein are couplers that improve the tolerance of misalignment when a single mode (SM) fiber is used as waveguide input. This enables the possibility of passive/automatic alignment and therefore reduces the production cost. The coupler also serves as a spot-size converter that reduces the spot size and is suitable for applications where a waveguide mode with small cross-section area is of particular importance. One such example can be a waveguide-based SiGe or III-V semiconductor photodetector in which the vertical size of its waveguide mode should be as small as few microns. | 09-29-2011 |
Yun-Chung N. Na, Palo Alto, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120126286 | MONOLITHIC THREE TERMINAL PHOTODETECTOR - Photodetectors operable to achieve multiplication of photogenerated carriers at ultralow voltages. Embodiments include a first p-i-n semiconductor junction combined with a second p-i-n semiconductor junction to form a monolithic photodetector having at least three terminals. The two p-i-n structures may share either the p-type region or the n-type region as a first terminal. Regions of the two p-i-n structures doped complementary to that of the shared terminal form second and third terminals so that the first and second p-i-n structures are operable in parallel. A multiplication region of the first p-i-n structure is to multiply charge carriers photogenerated within an absorption region of the second p-i-n structure with voltage drops between the shared first terminal and each of the second and third terminals being noncumulative. | 05-24-2012 |