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Na, Gyeonggi-Do
Byoung-Sun Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090290114 | DISPLAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME - A first slit pattern is formed in a display substrate and a display panel of vertical alignment mode having the display substrate. The first slit pattern includes slits, a pair of projections and a pair of notches. A divergence point where the slits meet each other and an incision portion of the slits have the same function as the pair of projections in the generation of a singular point of liquid crystal. A contact hole exposing a part of an output electrode of a switching element is formed at a protective layer of an array substrate. A step recess is formed at a protective layer corresponding to a storage electrode, a divergence point of the slits is arranged to correspond to the storage electrode. The singular point of the liquid crystal is induced to occur at a regular position, and thus afterimages and spots can be prevented. | 11-26-2009 |
| 20110186849 | TFT SUBSTRATE FOR DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed is a TFT substrate for a display apparatus comprising a gate wiring including a gate electrode, a data wiring including a data line, a source electrode connected to the data line, and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring, wherein the semiconductor layer under the drain electrode is disposed within an area overlapping the gate electrode and the semiconductor layer under the source electrode extends outward to an area not overlapping the gate electrode. Advantageously, the present disclosure provides a TFT substrate for a display apparatus having a high aperture ratio and causing less afterimaging, and a manufacturing method of the same. | 08-04-2011 |
| 20110304786 | DISPLAY SUBSTRATE - A display substrate includes a plurality of gate lines extending in a first direction and arranged in a second direction in a display area of the display substrate, an alignment film formed in the display area and in an end area adjacent to end portions of the gate lines in a peripheral area surrounding the display area, and a plurality of circuit stages formed in the end area to connect to the gate lines and a dummy stage connected to a last circuit stage of the circuit stages. Each of the circuit stages includes a gate driving circuit disposed at the higher portion the gate line corresponding to the circuit stages and a gate connecting line formed in the peripheral area between the display area and the gate driving circuit to connect each of the circuit stages with each of the gate lines. | 12-15-2011 |
Dong-Won Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090325614 | METHOD OF PROVIDING MULTIMEDIA MESSAGING SERVICE USING UNIQUE MESSAGE INDENTIFIER BACKGROUND OF THE INVENTION - The present invention relates to a method of providing a multimedia messaging service, which guarantees the uniqueness of a transmitted multimedia message. In the multimedia messaging method using a mobile communication network of the present invention, a multimedia message transmitted from an originating mobile station is stored. A receiving mobile station is informed of the arrival of the multimedia message. The stored multimedia message is transmitted to the receiving mobile station if a download request is received from the receiving mobile station. In this case, the stored multimedia message includes a unique message identifier distinguished from file information of other multimedia messages stored to be retransmissible. | 12-31-2009 |
Eun Sung Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090316513 | SEMICONDUCTOR MEMORY APPARATUS HAVING A SUB-WORD LINE DRIVER FOR INCREASING AN AREA MARGIN IN THE MEMORY CORE AREA - A semiconductor memory apparatus with a sub-word line driver is presented which has an increased area margin in the memory core area. The sub-word line driver is configured to operate in response to activation of a main word line and in response to positive and negative sub-word line enable signals. The sub-word line driver includes a pull-up driver and a pull-down driver. The pull-up driver is configured to pull-up drive a first sub-word line to the potential level of the positive sub-word line enable signal in response to the activation of the main word line. The pull-down driver is configured to pull-down drive the first sub-word line in response to the negative sub-word line enable signal. | 12-24-2009 |
| 20100309738 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a bit line pair electrically connected to a memory cell and a bit line sense amplifier for detecting and amplifying voltage levels of the bit line pair. The semiconductor memory apparatus is configured to perform a test to determine the occurrence of leakage current by deactivating the bit line sense amplifier and applying a test voltage to the bit line pair when the semiconductor memory apparatus is in test mode. | 12-09-2010 |
Gun-Pyo Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090003704 | METHOD AND SYSTEM FOR CONTROLLING BROWSER BY USING IMAGE - Browser controlling method and system using an image are provided. The method includes inputting an image; recognizing the image; and executing a command based on the recognized image. Accordingly, the command based on the user's input image can be executed in the browser. Also, since the browser does not need to display various function buttons, the screen can be utilized more efficiently. | 01-01-2009 |
Hai-Sub Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090191713 | METHOD OF FORMING FINE PATTERN USING BLOCK COPOLYMER - Provided is a method of forming a fine pattern using a block copolymer. The method comprises forming a coating layer including a block copolymer having a plurality of repeating units on a substrate. A mold is provided having a first pattern comprising a plurality of ridges and valleys. The first pattern is transferred from the mold into the coating layer. Then, a self-assembly structure is formed comprising a plurality of polymer blocks aligned in a direction guided by the ridges and valleys of the mold thereby rearranging the repeating units of the block copolymer within the coating layer by phase separation while the coating layer is located within the valleys of the mold. A portion of the polymer blocks are removed from among the plurality of polymer blocks and a self-assembly fine pattern of remaining polymer blocks is formed. | 07-30-2009 |
Ha Sun Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100201494 | SYSTEM AND METHOD FOR ALLOWING MULTIPLE RFID READER DEVICES TO READ RFID TAGS WITHOUT COLLISION - Provided are an RFID operating system and an RFID system operating method for allowing multiple RFID readers to read tags without collision. The RFID system operating method includes the steps of grouping RFID readers spaced apart by more than a spacing distance capable of avoiding collision between RFID readers into a single group to determine at least one group, classifying RPM readers included in each group into at least one sub-group based on a read time of each RFID reader, and driving the RFID readers such that RPM readers belonging to at least two different sub-groups that do not collide with each other simultaneously operate. According to the present invention, switching is performed sub-group by sub-group to reduce the number of switching operations and sub-groups can simultaneously operate to decrease a read time. | 08-12-2010 |
Hoonjoo Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100099245 | Methods of Forming Semiconductor Devices - Provided are a semiconductor device and a method of forming the same. The method may include forming a metal oxide layer on a substrate and forming a sacrificial oxide layer on the metal oxide layer. An annealing process is performed on the substrate. A formation-free energy of the sacrificial oxide layer is greater than a formation-free energy of the metal oxide layer at a process temperature of the annealing process. | 04-22-2010 |
Hoon-Joo Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100124805 | METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS USING NITRIDATION - A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer | 05-20-2010 |
Hye-Seok Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110085100 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE AND DISPLAY DEVICE HAVING THE DISPLAY SUBSTRATE - A display substrate includes a first pixel electrode and a second pixel electrode. The first pixel electrode includes a plurality of first electrode bars. A data line provides a data voltage to the first pixel electrode. The second pixel electrode includes a plurality of second electrode bars alternately disposed with the first electrode bars. A first power line is formed adjacent to a gate line to provide a first voltage to the second pixel electrode. A second power line crosses the first power line and is electrically connected to the first power line. A first switching element is electrically connected to the data line, the gate line and the first pixel electrode. A second switching element is electrically connected to the first power line, the gate line and the second pixel electrode. | 04-14-2011 |
Hyoung-Jun Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100315157 | SEMICONDUCTOR DEVICE - A semiconductor device is capable of generating an internal voltage having a voltage level that is dependent on an external power supply voltage. The semiconductor device includes an internal voltage generation unit configured to generate a plurality of internal voltages having different voltage levels by using an external power supply voltage, a voltage level detection unit configured to detect a voltage level of the external power supply voltage, and a selection unit configured to selectively output one of the internal voltages in response to a detection result of the voltage level detection unit. | 12-16-2010 |
| 20110006823 | SIGNAL DELAY CIRCUIT, CLOCK TRANSFER CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal. | 01-13-2011 |
Jong-Hoon Na, Gyeonggi-Do KR
Kee-Wook Na, Gyeonggi-Do KR
Ki-Su Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100048015 | Methods of Forming Void-Free Layers in Openings of Semiconductor Substrates - In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer. | 02-25-2010 |
Kun Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120058054 | GADOLINIUM COMPLEX, METHOD FOR PREPARING SAME, AND MRI CONTRAST AGENT COMPRISING SAME - Disclosed are a gadolinium complex formed by coordination of gadolinium to the diethylenetriaminepentaacetic acid dianhydride (DTPA) moiety of a pullulan-DTPA conjugate formed by an ester bond between pullulan and DTPA, a preparation method thereof, an MRI contrast composition comprising the complex, and a method of providing information for diagnosis of disease using the complex as an MRI contrast agent. The pullulan-DTPA-Gd complex has a long in vivo half-life, low toxicity, and high MRI signal intensity resulting in clear MRI images, compared to prior gadolinium complexes, indicating that it is advantageously used as an MRI contrast agent. In addition, it is possible to obtain MRI images allowing one to differentiate between diseased liver tissue and normal liver tissue, indicating that it is used as an MRI contrast agent for the liver. | 03-08-2012 |
Kwang-Jin Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100310029 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - A semiconductor memory apparatus includes a clock input unit configured to receive a system clock and a data clock, a data clock phase regulation unit configured to regulate a frequency of the data clock, and delay the data clock by a delay varied in accordance with a training information signal, and a clock phase comparison unit configured to compare a phase of an output clock of the data clock phase regulation unit with a phase of the system clock, and generate the training information signal according to a result of the comparison. | 12-09-2010 |
| 20110095797 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal. | 04-28-2011 |
| 20110148487 | DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal. | 06-23-2011 |
| 20110156784 | CLOCK DELAY CORRECTING DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code. The clock input unit is configured to receive a data clock. The clock phase mixing unit is configured to receive the data clock through the clock input unit and a delayed data clock, which is generated by delaying the data clock by a predetermined time, mix a phase of the data clock and a phase of the delayed data clock at a ratio corresponding to the impedance matching code, and output a phase-mixed data clock. The data input/output unit is configured to input/output a data signal in response to the phase-mixed data clock. | 06-30-2011 |
| 20120007647 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal, and a duty cycle correcting unit configured to output the output clock by driving an input clock to a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code. | 01-12-2012 |
| 20120106278 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a plurality of banks, a clock input unit configured to receive an external data clock, an internal data clock generation unit configured to receive the external data clock from the clock input unit and generate an internal data clock by delaying the external data clock by a delay amount which changes in correspondence to the number of banks activated among the plurality of banks, and a data buffer unit configured to buffer a data signal in response to the internal data clock. | 05-03-2012 |
Kyoung Hwan Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110214927 | BIDIRECTIONAL MOVING MICRO-ROBOT SYSTEM - Disclosed herein is a bidirectional moving micro-robot system. The bidirectional moving micro-robot system has a first body having a plurality of legs foldably/unfoldably connected thereto, a second body having a plurality of legs foldably/unfoldably connected thereto and a connection member having both end portions respectively connected to the first and second bodies. In the bidirectional moving micro-robot system, the length of the connection member exposed between the first and second bodies is extended or contracted. | 09-08-2011 |
Se-Wook Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090077304 | MEMORY SYSTEM HAVING NONVOLATILE AND BUFFER MEMORIES, AND READING METHOD THEREOF - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference. | 03-19-2009 |
| 20110289264 | Memory System Having Nonvolatile and Buffer Memories, and Reading Method Thereof - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference. | 11-24-2011 |
Su Hyun Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110007086 | METHOD AND APPARATUS FOR VIRTUAL OBJECT BASED IMAGE PROCESSING - Virtual object based image processing method and apparatus are provided. At least one virtual object is selected and applied to the underlying image such as a preview image obtained by a camera in order to create a merged image. The selected virtual object has a modification attribute allowing parts of the underlying image to be modified. A user can easily obtain various merged images decorated with the modification attributes of the selected virtual object by checking in advance merged images overlapped with the virtual object before saving them. | 01-13-2011 |
| 20110041086 | USER INTERACTION METHOD AND APPARATUS FOR ELECTRONIC DEVICE - An interaction method and apparatus for an electronic device is proposed for providing the user with interactive audio/video/haptic effects. An interaction method for an electronic device according to the present invention includes outputting an event object in response to an input action to an event element; detecting a user interaction to the event object; and outputting an effect object in response to the user interaction. | 02-17-2011 |
Sung Min Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100101730 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus, which is designed to prevent the wobbling of a rotational shaft rotating, is provided. The substrate includes a rotation shaft and a connecting member. A unit is disposed between the rotational shaft and the connecting member to make the rotational shaft and the connecting member close-contact each other or a unit is disposed under the rotational shaft to prevent the wobbling of the rotational shaft. | 04-29-2010 |
Sung Wook Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090142635 | Coolant temperature controller for fuel cell vehicle - A coolant temperature controller for a fuel cell vehicle comprises: a housing including first and second inlet ports provided on one side thereof and an exhaust port provided on the other side thereof in a horizontal direction with respect to the first inlet port; a plunger operating portion including an operating plunger for capable of vertical movement between the first and second inlet ports and the exhaust port of the housing to proportionally control degree of opening of the first and second inlet ports; a motor mounted on the top of the plunger operating portion; and a motor shaft connected to the motor and extending from the motor to the bottom of the plunger operating portion to be connected to the operating plunger, wherein the vertical movement of the operating plunger is driven by a rotational force transmitted through the motor shaft as the motor operates. The controller can maintain the coolant at a preset temperature for optimal operation of the fuel cell stack. | 06-04-2009 |
| 20090151903 | Coolant reservoir tank for fuel cell vehicle - The present invention provides a coolant reservoir tank for a fuel cell vehicle, in which the coolant reservoir tank is positioned at a bottom of the vehicle such that coolant in a coolant line is collected in the reservoir tank by gravity during shutdown of a fuel cell system and the coolant in the reservoir tank is supplied to the coolant line by a vacuum pump during startup of the fuel cell system. | 06-18-2009 |
| 20100116363 | WATER RESERVOIR FOR VEHICLE HAVING DRAIN VALVE OPERATED BY TRAVELING WIND - The present invention provides a cooling water reservoir for a fuel cell vehicle, in which a drain valve operated by traveling wind is mounted in a reservoir housing of the reservoir such that unnecessary water in an amount corresponding to the amount of product water, generated in the fuel cell stack during operation of a fuel cell system and flowing in the reservoir housing, can be discharged through the drain valve automatically in real-time, thus preventing the water in the reservoir housing from overflowing due to the inflow of the product water generated in the fuel cell stack during operation of the fuel cell system. | 05-13-2010 |
Young-Jun Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090247524 | HSP90 Inhibitor - Compounds represented by formula (1) shown below, pharmaceutically acceptable salts thereof, and pharmaceutical compositions comprising such compounds are provided. | 10-01-2009 |
Youn-Ho Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090050661 | Glass Cutting Apparatus With Bending Member and Method Using Thereof - Disclosed herein is glass cutting apparatuses and methods of cutting glass using the glass cutting apparatuses. More particularly, disclosed is a glass cutting apparatus which cuts a glass sheet ( | 02-26-2009 |
Yun-Whan Na, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120133263 | LIGHT EMITTING DIODE (LED) LAMP - A light emitting diode (LED) lamp includes an emission unit comprising one or more LED light-emitting devices and a circuit substrate whereon the one or more LED light-emitting devices are mounted; a heat dissipating member whereon the emission unit is mounted and that dissipates heat generated by the emission unit; and a light-transmitting lamp cover directly contacting the heat dissipating member and coupled with the heat dissipating member so as to cover the emission unit, wherein the lamp cover is formed of a light-transmitting material having a thermal conductivity equal to or greater than 9 W/m·K | 05-31-2012 |
| 20120134158 | LIGHT EMITTING DIODE (LED) LAMP - A light emitting diode (LED) lamp includes an emission unit comprising one or more LED light-emitting devices and a circuit substrate whereon the one or more LED light-emitting devices are mounted; a heat dissipating member whereon the emission unit is mounted and that dissipates heat generated by the emission unit; and a light-transmitting lamp cover directly contacting the heat dissipating member and coupled with the heat dissipating member so as to cover the emission unit, wherein the lamp cover is formed of a light-transmitting material having a thermal conductivity equal to or greater than 9 W/m·K | 05-31-2012 |