Patent application number | Description | Published |
20100123258 | Low Temperature Board Level Assembly Using Anisotropically Conductive Materials - An integrated circuit may be secured to a substrate using an anisotropically conductive adhesive that may be cured at a temperature of less than 150° C. In some embodiments, an acrylic resin with embedded metallic particles may be used as the anisotropically conductive adhesive. In some embodiments, the board level reliability of the resulting product may be improved through the use of the anisotropically conductive adhesive that may be cured at a temperature of less than 150° C. | 05-20-2010 |
20100148359 | Package on Package Assembly using Electrically Conductive Adhesive Material - Packages are joined together using an anisotropic conductive material that includes an electrically insulative component and a plurality of electrically conductive particles. The electrically conductive particles may complete electrical connection between inter-package connectors and bond pads that may otherwise fail. The electrically insulative component may be cured to act as an underfill to provide mechanical connection between the packages. | 06-17-2010 |
20100155934 | MOLDING COMPOUND INCLUDING A CARBON NANO-TUBE DISPERSION - A molding compound comprising a resin, a filler, and a carbon nano-tube dispersion is disclosed. The carbon nano-tube dispersion achieves a low average agglomeration size in the molding compound thereby providing desirable electromechanical properties and laser marking compatibility. A shallow laser mark may be formed in a mold cap with a maximum depth of less than 10 microns. | 06-24-2010 |
20100164083 | PROTECTIVE THIN FILM COATING IN CHIP PACKAGING - A protective thin film coating for device packaging. A dielectric thin film coating is formed over die and package substrate surfaces prior to applying a molding compound. The protective thin film coating may reduce moisture penetration from the bulk molding compound or the interface between the molding compound and the die or substrate surfaces. | 07-01-2010 |
20100164085 | MULTI-DIE BUILDING BLOCK FOR STACKED-DIE PACKAGE - A multi-die building block for a stacked-die package is described. The multi-die building block includes a flex tape having a first surface and a second surface, each surface including a plurality of electrical traces. A first die is coupled, through a first plurality of interconnects, to the plurality of electrical traces of the first surface of the flex tape. A second die is coupled, through a second plurality of interconnects, to the plurality of electrical traces of the second surface of the flex tape. | 07-01-2010 |
20100167466 | SEMICONDUCTOR PACKAGE SUBSTRATE WITH METAL BUMPS - An apparatus and method of making a package substrate with metal bumps is presented. The package substrate comprises a substrate base and a plurality of metal bumps which are formed on the substrate base. A microelectronic die may thereafter be attached to the package substrate. Also presented is a method for attaching the package substrate to a printed circuit board (PCB). | 07-01-2010 |
20110127642 | PACKAGE INCLUDING AT LEAST ONE TOPOLOGICAL FEATURE ON AN ENCAPSULANT MATERIAL TO RESIST OUT-OF-PLANE DEFORMATION - Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, including a die and an encapsulant material formed over the die, and at least one topological feature formed on an external surface of the encapsulant material, and configured to resist out-of-plane deformation of the package. Other embodiments may be described and claimed. | 06-02-2011 |
20110128711 | PACKAGE INCLUDING AN UNDERFILL MATERIAL IN A PORTION OF AN AREA BETWEEN THE PACKAGE AND A SUBSTRATE OR ANOTHER PACKAGE - Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed. | 06-02-2011 |
20130258578 | PACKAGE INCLUDING AN UNDERFILL MATERIAL IN A PORTION OF AN AREA BETWEEN THE PACKAGE AND A SUBSTRATE OR ANOTHER PACKAGE - Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed. | 10-03-2013 |