Patent application number | Description | Published |
20090154278 | MEMORY DEVICE WITH SELF-REFRESH OPERATIONS - An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh. | 06-18-2009 |
20120201085 | LOW POWER MEMORY CONTROL CIRCUITS AND METHODS - Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors. | 08-09-2012 |
20140071770 | Burst Sequence Control And Multi-Valued Fuse Scheme In Memory Device - A decoder circuit, responsive to a burst sequence control signal, for accessing a memory location in a memory array. The decoder circuit receives an address signal and outputs a plurality of first select lines. Logic circuitry receives these first select lines and a burst sequence control signal and outputs a plurality of second select lines. When the bust sequence control signal is unasserted, the logic circuitry passes through to the plurality of second select lines the signals received on the plurality of first select lines. When the burst sequence control signal is asserted, the logic circuitry performs a logical operation on the signals received on the plurality of first select lines and outputs the result on the plurality of second select lines. | 03-13-2014 |
Patent application number | Description | Published |
20100315879 | PAGE BUFFER OF NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING PROGRAM VERIFICATION OPERATION USING THE SAME - A page buffer of a nonvolatile memory device comprises a sense unit coupled between the sense node and the bit lines of a memory cell array, comprising a number of memory cells, and configured to precharge the bit lines to different voltage levels in response to a page buffer sense signal of a first or second voltage level, a MUX unit configured to output the page buffer sense signal of the first or second voltage level in response to a control signal according to a value of program data, a flag latch configured to temporarily store the program data and to output the control signal to the MUX unit, and a main latch configured to sense the voltage levels of the bit lines via the sense node and to perform a program verification operation. | 12-16-2010 |
20120008408 | NON-VOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME - A non-volatile memory device and an operation method of the same are provided. A method for operating a non-volatile memory device includes programming a plurality of memory cells based on a target voltage level, verifying threshold voltage levels of the plurality of memory cells based on a correction voltage level higher than the target voltage level and selecting a memory cell programmed lower than the correction voltage level, and programming the selected memory cell based on the correction voltage level. | 01-12-2012 |
20120099378 | NONVOLATILE MEMORY AND METHOD FOR VERIFYING THE SAME - A nonvolatile memory device includes a cell string including a plurality of memory cells connected in series, a bit line connected to the cell string, a voltage sensing unit configured to apply a verify precharge voltage to the bit line in response to a voltage of a sensing node before a verify operation, a voltage transmission unit configured to apply a voltage of the bit line to the sensing node in a verify operation, and a page buffer configured to determine a voltage of the sensing node in response to data stored therein before a verify operation and to change the data in response to a voltage level of the sensing node in the verify operation. | 04-26-2012 |
20120198290 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A method for performing a program operation in a non-volatile memory device includes applying a programming pulse to a plurality of memory cells, verifying whether the plurality of the memory cells are programmed to produce a verification result, determining whether all of the plurality of the memory cells are programmed in response to the verification result to produce a first determination result and determining whether at least a first number of memory cells are programmed among the plurality of the memory cells in response to the first determination result to produce a second determination result. | 08-02-2012 |
20120269010 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node. | 10-25-2012 |
20120269020 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a second word line group of the word lines in response to a result of the determining, and performing a program operation on the selected word line. | 10-25-2012 |
Patent application number | Description | Published |
20120164365 | VACUUM INSULATION PANEL AND METHOD FOR MANUFACTURING THE SAME - A vacuum insulation panel and to a method for manufacturing same. The method comprises: (a) a step of laminating a plurality of glass fiber boards to form a core, wherein the glass fiber boards are produced by a papermaking method using glass fiber dispersed in an inorganic binder; (b) a step of forming an outer cover having a structure in which a surface protection layer, a metal barrier layer, and an adhesive layer are laminated; (c) a step of producing a getter by packing quicklime (CaO) powder in a pouch; (d) a step of attaching the getter onto the core, or inserting the getter into the surface of the core; and (e) a step of forming the outer cover into a bag body, inserting the core from step (d) into the bag body, and sealing the bag body, thereby improving long-term durability of the vacuum insulation panel. | 06-28-2012 |
20120231204 | GROOVED TYPE VACUUM THERMAL INSULATION MATERIAL AND A PRODUCTION METHOD FOR THE SAME - The present invention relates to a groove-type vacuum insulation material and a method of manufacturing the same. The groove-type vacuum insulation material includes core materials each having a block shape, at least one lateral wall of which has an inclined surface; a groove-type insulation board, in which the core materials are arranged on a plane of the board to be separated from each other, with the inclined surfaces thereof facing each other; an outer skin material formed in a film pouch shape and surrounding the entirety of upper and lower sides of the groove-type insulation board, the outer skin material being brought into close contact with the groove-type insulation board by vacuum-sealing, and exhibiting bending characteristics in a space between the core materials. The present invention also relates to a method of manufacturing the same. | 09-13-2012 |
20130287978 | VACUUM INSULATION MATERIAL INCLUDING AN INNER BAG, AND METHOD FOR MANUFACTURING SAME - The present invention relates to a vacuum insulation material including an inner bag and to a method for manufacturing same. The method for manufacturing the vacuum insulation material includes: a step of manufacturing a core material; a step of compressing and packing the entire surface of the core material using an inner bag made of a breathable film material; a step of disposing a getter on the upper portion of the inner bag; and a step of vacuum-packing a covering material on the upper portion of the inner bag. The inner bag is made of polypropylene (PP), polyester (PET), and/or polyethylene. Since the inner bag is manufactured using a breathable film having fine holes, the method for manufacturing the vacuum insulation material may have improved efficiency, and the vacuum insulation material may be improved in terms of the long-term durability and vacuum insulation properties thereof. | 10-31-2013 |
20140034868 | GLASS FIBERBOARD AND PRODUCTION METHOD THEREFOR - The present invention relates to a glass fiberboard and to a production method therefor, and more specifically, to technology for providing a glass fiberboard for vacuum heat insulation and a production method therefor, which have outstanding initial heat insulation performance and economic advantages through application of an optimized inorganic binder. | 02-06-2014 |
20140166926 | VACUUM INSULATION MATERIAL INCLUDING COMPOSITE GETTER MATERIAL - The present invention relates to a vacuum insulation material using a getter material obtained by mixing zeolite and calcium oxide, and more particularly, to a vacuum insulation material in which zeolite having a large specific surface area to absorb the greater part of remaining water from the vacuum insulation material is mixed with calcium oxide and used as a getter material, thereby achieving improved initial thermal conductivity. | 06-19-2014 |