| Patent application number | Description | Published |
|---|
| 20100133598 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material. | 06-03-2010 |
| 20100133599 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 06-03-2010 |
| 20100163968 | SEMICONDUCTOR MEMORY DEVICE HAVING INSULATION PATTERNS AND CELL GATE PATTERNS - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening. | 07-01-2010 |
| 20100178759 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. | 07-15-2010 |
| 20110045657 | METHOD FOR FABRICATING REWRITABLE THREE-DIMENSIONAL MEMORY DEVICE - A method for fabricating a three-dimensional semiconductor memory device including three-dimensionally arranged transistors includes forming a thin film structure comprising a plurality of thin films on a semiconductor substrate, patterning the thin film structure such that a penetration region is formed to expose the semiconductor substrate, forming a polycrystalline semiconductor layer to cover the resultant structure where the penetration region is formed, patterning the semiconductor layer to locally form a semiconductor pattern within the penetration region, and performing a post-treatment process to treat the semiconductor layer or the semiconductor pattern with a post-treatment material containing hydrogen or deuterium. | 02-24-2011 |
| 20110101443 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern. | 05-05-2011 |
| 20110186851 | MULTILAYER SEMICONDUCTOR DEVICES WITH CHANNEL PATTERNS HAVING A GRADED GRAIN STRUCTURE - Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing. | 08-04-2011 |
| 20110248327 | Three-Dimensional Semiconductor Memory Devices and Methods of Forming the Same - Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells. | 10-13-2011 |
