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Muth, NY
Robert Muth, New York, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110029961 | NATIVE CODE MODULE SECURITY FOR ARM INSTRUCTION SET ARCHITECTURES - Some embodiments provide a system that executes a native code module. During operation, the system obtains the native code module. Next, the system loads the native code module into a secure runtime environment. Finally, the system safely executes the native code module in the secure runtime environment by using a set of software fault isolation (SFI) mechanisms that constrain store instructions in the native code module. The SFI mechanisms also maintain control flow integrity for the native code module by dividing a code region associated with the native code module into equally sized code blocks and data blocks and starting each of the data blocks with an illegal instruction. | 02-03-2011 |
Tamara Jean Muth, Ballston Lake, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090130304 | METHODS OF FORMING COMPOSITE POWDER COATINGS AND ARTICLES THEREOF - A method of forming a composite powder coating comprises depositing multiple layers of a powder coating composition onto a substrate, wherein adjacent layers are formed of a different powder coating composition; and curing the multiple layers of the powder coating composition in a single thermal curing step. The layers can be used to protect power generation equipment from aqueous corrosion, particle erosion, slurry erosion, fretting, and foulig. | 05-21-2009 |
| 20090297720 | EROSION AND CORROSION RESISTANT COATINGS, METHODS AND ARTICLES - Disclosed herein is an erosion and corrosion resistant coating comprising a metallic binder, a plurality of hard particles, and a plurality of sacrificial particles. Also disclosed is a method of improving erosion and corrosion resistance of a metal component comprising disposing on a surface of the metal component the foregoing erosion and corrosion resistant coating comprising, and a metal component comprising a metal component surface and the foregoing erosion and corrosion resistant coating comprising a first surface and a second surface opposite the first surface, wherein the first surface is disposed on the metal component surface. | 12-03-2009 |
| 20100304084 | PROTECTIVE COATINGS WHICH PROVIDE EROSION RESISTANCE, AND RELATED ARTICLES AND METHODS - A coating composition is described, having a first coating layer which includes a metallic matrix in which metal carbide particles are dispersed; and a hard, dense second coating layer disposed over the first coating layer. The second coating layer is formed from a metal nitride-type material, and has an average roughness of less than about 80 micro-inches (Ra). Related articles and processes are also disclosed. | 12-02-2010 |
| 20100304181 | PROTECTIVE COATINGS WHICH PROVIDE EROSION RESISTANCE, AND RELATED ARTICLES AND METHODS - A coating composition is described, having a first coating layer which includes a nickel-chromium matrix in which metal carbide particles are dispersed; and a hard, dense second coating layer disposed over the first coating layer. The second coating layer is formed from a metal nitride-type material, and has an average roughness of less than about 80 micro-inches (Ra). Related articles and processes are also disclosed. | 12-02-2010 |
| 20110008614 | Electrostatic Powder Coatings - In one embodiment, a protective coating may be electrostatically applied to a rotary machine component. The powder coating includes an electrically conductive sacrificial base coat and a ceramic oxide erosion resistant top coat. | 01-13-2011 |
| 20110076413 | SINGLE LAYER BOND COAT AND METHOD OF APPLICATION - A protective coating system for metal components includes a superalloy metal substrate, such as a component of a gas turbine. A single layer bond coat is applied to the superalloy metal substrate in a thermal spray process from a homogeneous powder composition having a particle size distribution wherein about 90% of the particles by volume are within a range of about 10 pan to about 100 μm. The percentage of particles within any 10 μm band within the range does not exceed about 20% by volume, and the percentage of particles within any two adjacent 10 μm bands within the range does not deviate by more than about 8% by volume. | 03-31-2011 |
William Muth, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110102760 | ALIGNMENT METHOD FOR SEMICONDUCTOR PROCESSING - A method provides improved alignment for a photolithographic exposure. In such method, a first exposure tool and a first chuck used in a reference photolithographic exposure of a first material layer on a substrate can be identified. The substrate typically includes at least a semiconductor layer. The first chuck typically is one of a plurality of chucks usable with the first exposure tool. The method may further include identifying a second exposure tool and a second chuck used in a current photolithographic exposure of a second material layer on the substrate. In one embodiment, alignment correction information specific to each of the identified first exposure tool, the first chuck, the second exposure tool and the second chuck can be used in aligning the semiconductor substrate to a second exposure tool and a second chuck. In one embodiment, such method can compensate for alignment error caused by differences between the first and second exposure tools, between the first and second chucks, or between the first and second exposure tools and between the first and second chucks. | 05-05-2011 |
William A. Muth, Lagrangeville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090053627 | METHODS AND SYSTEMS FOR NORMALIZING ERROR - A method for fabricating parts using a photolithography system, includes: performing a search of normalization data for an estimated dose operating point; and using the estimated dose operating point for fabrication of new parts. Other methods are provided. | 02-26-2009 |
| 20090186286 | Method To Control Semiconductor Device Overlay Using Post Etch Image Metrology - A method of determining positioning error between lithographically produced integrated circuit patterns on at least two different lithographic levels of a semiconductor wafer comprising. The method includes exposing, developing and etching one or more lithographic levels to create one or more groups of marks comprising a target at one or more wafer locations. The method then includes exposing and developing a subsequent group of marks within the target on a subsequent lithographic level. The method then comprises measuring the position of the marks on each level with respect to a common reference point, and using the measured positions of the groups of marks to determine the relative positioning error between one or more pairs of the developed and etched lithographic levels on which the marks are located. | 07-23-2009 |
| 20100145646 | Predicting Wafer Failure Using Learned Probability - Techniques for estimating a quality of one or more wafers are presented. One or more first wafers comprising one or more first dies are tested. A probability of wafer failure is determined in accordance with one or more first test measurements of the one or more first dies. A pass status and/or a fail status of one or more second wafers is inferred by testing a select one or more second dies of the one or more second wafers and evaluating one or more second test measurements of the select one or more second dies in accordance with the determined probability of wafer failure. | 06-10-2010 |