Patent application number | Description | Published |
20080253218 | Column decoder and semiconductor memory apparatus using the same - A column decoder according includes: a plurality of main decoding units coupled to different memory banks that decode a pre-decoding signal and output column selection signals to the corresponding memory banks; and one or more pre-decoders, having a lesser number than the main decoders, which generates and outputs the pre-decoding signal by decoding the column address and the bank information signal. | 10-16-2008 |
20090190419 | CIRCUIT AND METHOD FOR CONTROLLING SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY APPARATUS - A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal. | 07-30-2009 |
20090303808 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator configured to generate a main strobe signal by controlling the reference pulse width in response to the reference strobe signal and a bank grouping signal that is activated in a bank grouping mode where columns are continuously accessed in a plurality of logically grouped banks. | 12-10-2009 |
20100246296 | Write Driver and Semiconductor Memory Device Using the Same - A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals. | 09-30-2010 |
20100309744 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABILITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 12-09-2010 |
20110002179 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. | 01-06-2011 |
20110103163 | MULTI-BIT TEST CONTROL CIRCUIT - A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test. | 05-05-2011 |
20120014204 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABLITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 01-19-2012 |
20120014205 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABILITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 01-19-2012 |
20130148449 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. | 06-13-2013 |
20130257520 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes: a first driving voltage generation unit configured to generate a first driving voltage; a fuse unit coupled between an output node for receiving the first driving voltage and a fuse state sensing node; a driving unit configured to drive the fuse state sensing node with a second driving voltage in response to a control signal; a voltage level control unit configured to generate a voltage level control signal in response to a fuse state sensing signal that corresponds to a voltage level of the fuse state sensing node; and a second driving voltage generation unit configured to control and output a voltage level of the second driving voltage in response to the voltage level control signal. The semiconductor device repeatedly performs a rupture operation by monitoring a fuse state sensing signal. | 10-03-2013 |
20140185399 | TEST MEDIATION DEVICE AND SYSTEM AND METHOD FOR TESTING MEMORY DEVICE - A system for testing a memory device includes a memory device configured to include a plurality of memory cells, receive a test information having a first frequency, access memory cells corresponding to an address included in the test information, and activate a fail signal if fail occurs in the memory cells corresponding to the address, a test device configured to generate a test information having a second frequency different from the first frequency, and a test mediation device configured to generate the test information having the first frequency and the address based on the test information having the second frequency and the fall signal and store the address corresponding to the fail memory cells in response to the fail signal as a fail address. | 07-03-2014 |