Patent application number | Description | Published |
20100038741 | SEMICONDUCTOR APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS, AND CAMERA MODULE - A semiconductor apparatus includes, a semiconductor substrate having first and second main surfaces and a thought hole connecting the first and second main surfaces; a first insulation layer arranged on the first main surface, and having an opening corresponding to the thought hole; a first conductive layer arranged on the first insulation layer, and covering the thought hole; a second insulation layer arranged on an inner wall of the thought hole and the second surface; a second conductive layer arranged in the thought hole and on the second insulation layer, the second conductive layer contacting the first conductive layer; and a filling member arranged on the second conductive layer in the through hole, and having a gap between the second conductive layer on the first main surface side. | 02-18-2010 |
20110073975 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND MANUFACTURING METHODS THEREOF - According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface at an opposite side thereof. The first surface has an active layer with a light-receiving part. The semiconductor device also includes an adhesive layer provided to surround the light-receiving part on the first surface of the semiconductor substrate; a light-transmissive protective member disposed above the light-receiving part of the semiconductor substrate with a predetermined gap and adhered via the adhesive layer; and plural external connection terminals arranged in a predetermined array on the second surface of the semiconductor substrate are included. Each center point of the external connection terminals forming two facing edges is positioned inside of an area of the adhesive layer projected on the second surface among the outermost external connection terminals. | 03-31-2011 |
20120001324 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a circuit substrate, and first and second semiconductor chips mounted on it. The first semiconductor chip and the second semiconductor chip are flip-chip connected, and an underfill resin is filled between them. The underfill resin has a fillet portion. A thickness T | 01-05-2012 |
20120326339 | SEMICONDUCTOR DEVICE, AND METHOD AND APPARATUS FOR MANUFACTURING THE SAME - According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. | 12-27-2012 |
20150069437 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded. | 03-12-2015 |
Patent application number | Description | Published |
20110263076 | Stacked semiconductor device - A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 μm or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less. | 10-27-2011 |
20130313588 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor light emitting device includes a semiconductor layer having a light emitting layer. The device also includes a p-side electrode provided on a first region including the light emitting layer; an n-side electrode provided on a second region layer not including the light emitting layer; and a first insulating film having a first opening communicating with the p-side electrode and a second opening communicating with the n-side electrode. A p-side interconnection is provided on the first insulating film and electrically connected to the p-side electrode through the first opening. An n-side interconnection is provided on the first insulating film and electrically connected to the n-side electrode through the second opening. The p-side interconnection has a plurality of protrusive parts protruding toward the n-side interconnection, and the n-side interconnection has a plurality of portions extending between the protrusive parts of the p-side interconnection. | 11-28-2013 |
20150069634 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip. | 03-12-2015 |
Patent application number | Description | Published |
20130333569 | HYDROGEN SEPARATION DEVICE - The hydrogen separation device comprises a laminate formed by laminating and integrating a hydrogen separation layer, a mixed gas layer kept adjacent to one surface of the hydrogen separation layer and having a mixed gas flow path, and a transmitted gas layer kept adjacent to the other surface of the hydrogen separation layer and having a transmitted gas flow path, and a vessel containing the laminate therein and filled with a buffer gas, wherein a buffer space is provided between the laminate and the inner wall of the vessel in which a buffer gas can reach at least one end face of the laminate in the lamination direction, and wherein the pressure in the buffer space is equal to or higher than the higher one of the pressure in the mixed gas flow path and the pressure in the transmitted gas flow path. | 12-19-2013 |
20150214457 | THERMOELECTRIC MATERIAL AND THERMOELECTRIC MODULE - A thermoelectric material is manufactured by a manufacturing process including annealing at an annealing temperature from 125° C. to 200° C. and for an annealing time from 5 minutes to 12 hours applied to a substance selected from the group consisting of conductive polymer, polystyrene sulfonate (PSS), tosylate (TOS), chloride and perchlorate and a substance as solvent selected from the group consisting of ethylene glycol, ethanol, dimethyl sulfoxide and isopropanol. | 07-30-2015 |
20150369720 | APPARATUS AND METHOD FOR EVALUATING GAS BARRIER PROPERTIES - An apparatus for evaluating gas barrier properties, containing a polymer-containing support for supporting a sample, a chamber on a permeation side, and a detection unit, in which the support is connected with an opening of the chamber on the permeation side, and in which glass transition point of the polymer contained in the support is 100° C. or higher. | 12-24-2015 |
20160003726 | APPARATUS AND METHOD FOR EVALUATING GAS BARRIER PROPERTIES - An apparatus for evaluating gas barrier properties, containing a support ( | 01-07-2016 |
Patent application number | Description | Published |
20090089489 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND CONTROL METHOD OF FLASH MEMORY - The memory controller updates a count number based on a new assignment of a logical block to a physical block, and writes count information in the physical block to which the logical block is newly assigned. The count information is defined by the count number. The memory controller decides, based on the count number and the count information stored in each physical block, whether or not to transfer stored data in a physical block to another physical block. | 04-02-2009 |
20100205356 | MEMORY CONTROLLER, MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - In the control of the number of program-erase cycles, physical blocks (PBs) are divided into plural groups on a basis of the number of program-erase cycles and a search for a free PB is performed in the groups when assigning a logical block (LB) to the free PB. In the search, a free PB among a group covering a small number of program-erase cycles precedes that among a group covering a large number of program-erase cycles. Further, when searching out a free PB in the search, data stored in a PB (source PB) included in a group covering a smaller number of program-erase cycles than that covered by a group including the free PB searched out are transferred to the free PB if there is the source PB. The source PB is a PB to which a LB is assigned earliest among a group including it. | 08-12-2010 |
20100205357 | MEMORY CONTROLLER, MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - In the control of the number of program-erase cycles, when assigning a logical block (LB) to a physical block (PB), the number of program-erase cycles of a first PB and that of a second PB are compared, which first PB is a free PB of which the number of program-erase cycles is the smallest among that of free PBs, which second PB is a PB earliest assigned a LB among PBs each assigned a LB. As a result, in a case where the number of program-erase cycles of the first PB is larger by a predetermined value or more than that of the second PB, data stored in the second PB are transferred to a free PB of which the number of program-erase cycles is the largest among free PBs, and then the LB is assigned to the second PB. | 08-12-2010 |
20100211723 | Memory controller, memory system with memory controller, and method of controlling flash memory - Access to flash memories is controlled so that efficiency of data writing and effective utilization of storage area go together. In the access control, priority order, for physical blocks each storing effective data, is managed so that a position of a physical block in the assignment order becomes higher according as assignment of a logical block to the physical block is performed more recently. When assigning a logical block to a free physical block, a determination is made whether a position of a previous physical block is higher than a predetermined position in the priority order. The previous physical block is a physical block, then, corresponding to the same logical block as the free physical block. When the determination is negative, effective data stored in the previous physical block is transferred to the free physical block. | 08-19-2010 |
20110283052 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - The object of the present invention is to efficiently perform access to a physical block corresponding to a logical block often designated by an access request. To realize it, predetermined number of pieces of logical block information each for access to a physical block corresponding to logical block, until then, designated by an access request is held. In holding the predetermined pieces of logical block information, a piece of logical block information having high priority precede a piece of logical block information having low priority in priority order. In management of the priority order, priority of a piece of logical block information corresponding to a logical block often designated by an access request becomes high. When an access request is received, if logical block information corresponding to the logical block designated by the access request is held, access to the physical block corresponding to the designated logical block is performed based on the held logical block information. | 11-17-2011 |