| Patent application number | Description | Published |
|---|
| 20090026492 | LATERAL JUNCTION BREAKDOWN TRIGGERED SILICON CONTROLLED RECTIFIER BASED ELECTROSTATIC DISCHARGE PROTECTION DEVICE - The components of a silicon controlled rectifier, which are a p-doped anode, an n-well middle region, a p-well middle region, and an n-doped cathode, are formed along sidewalls and a bottom surface of a shallow trench isolation structure. The p-doped anode and the n-doped cathode are formed directly underneath a top surface of a silicon substrate. A trigger mechanism that provides an instantaneous turn-on current to latch the silicon controlled rectifier to an on-state is also provided. The trigger mechanism provides a temporary surge in the voltage of the p-doped middle region, causing the instantaneous turn-on current to flow from the p-doped middle region to the n-doped cathode. Combined with the proximity of the p-doped anode to the n-doped cathode, the trigger mechanism provides a fast turn on and a short low resistance current path for the electrostatic discharge protection circuit. | 01-29-2009 |
| 20090231766 | ELETROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING - A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry. | 09-17-2009 |
| 20100181621 | SIGNAL AND POWER SUPPLY INTEGRATED ESD PROTECTION DEVICE - An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure. | 07-22-2010 |
| 20100246076 | Electrical Overstress Protection Circuit - A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond. | 09-30-2010 |
| 20100265622 | ROBUST ESD PROTECTION CIRCUIT, METHOD AND DESIGN STRUCTURE FOR TOLERANT AND FAILSAFE DESIGNS - A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event. | 10-21-2010 |
| 20110286135 | Silicon Controlled Rectifier Based Electrostatic Discharge Protection Circuit With Integrated JFETS, Method Of Operation And Design Structure - An enhanced turn-on time SCR based electrostatic discharge (ESD) protection circuit includes an integrated JFET, method of use and design structure. The enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit includes an integrated JFET in series with an NPN base. | 11-24-2011 |
| 20120043583 | LOW LEAKAGE, LOW CAPACITANCE ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECITIFER (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURE - A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction. | 02-23-2012 |
| 20120091530 | Low trigger voltage electrostatic discharge NFET in triple well CMOS technology - An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type. | 04-19-2012 |
