Patent application number | Description | Published |
20080302024 | Tunable impedance load-bearing structures - A tunable impedance load bearing structure includes a support comprising an active material configured for supporting a load, wherein the active material undergoes a change in a property upon exposure to an activating condition, wherein the change in the property is effective to change an impedance characteristic of the support. | 12-11-2008 |
20110061310 | TUNABLE IMPEDANCE LOAD-BEARING STRUCTURES - A tunable impedance load bearing structure includes a support comprising an active material configured for supporting a load, wherein the active material undergoes a change in a property upon exposure to an activating condition, wherein the change in the property is effective to change an impedance characteristic of the support. | 03-17-2011 |
20110181073 | PEDESTRIAN IMPACT MITIGATION SYSTEM AND METHOD OF USE - A system for and method of mitigating pedestrian impact utilizing an energy absorption member, such as an expandable honeycomb celled matrix, and at least one tether disposed within a recessed formation defined by the vehicle and interconnected to the member and a drive mechanism, wherein the member is selectively caused to extend and be spaced from an exterior surface. | 07-28-2011 |
20120098244 | METHODS OF PREVENTING OR REDUCING THE AFFECTS OF ROOF IMPACT IN AUTOMOTIVE APPLICATIONS - A method of autonomously preventing or reducing the affects of roof impact in automotive applications, including the steps of determining a vehicle condition indicative of an imminent roof impact, and modifying a vehicular seat or roof structure, or deploying a netting as a result thereof, wherein active material actuation is preferably utilized to effect the same. | 04-26-2012 |
20120161921 | TUNABLE IMPEDANCE LOAD-BEARING STRUCTURES - A tunable impedance load bearing structure includes a support comprising an active material configured for supporting a load, wherein the active material undergoes a change in a property upon exposure to an activating condition, wherein the change in the property is effective to change an impedance characteristic of the support. | 06-28-2012 |
20150307044 | ARCHITECTED AUTOMOTIVE IMPACT BEAM - A curved sandwich impact structure for a vehicle having a micro-truss core. In one embodiment, the sandwich impact structure includes a micro-truss layer sandwiched between two facesheets, a micro-truss layer designed for energy absorption on the outside of one of the facesheets, and a fascia panel in contact with the energy absorbing micro-truss layer. | 10-29-2015 |
20160129865 | LOCAL ENERGY ABSORBER - A vehicle hood covering an underhood object includes an inner surface of the vehicle hood facing the underhood object and spaced from the underhood object, and an outer surface of the vehicle hood opposite the inner surface. A local energy absorber is operatively attached to the inner surface of the vehicle hood. The local energy absorber is a multiply-connected structure. The local energy absorber includes a wall defining an interior surface having symmetry about a central plane normal to the inner surface of the vehicle hood. A plurality of apertures is defined in the wall symmetrically about the central plane to initiate buckling and fracture in the wall during an impact applied to the outer surface defining an impact event having a duration of less than 20 milliseconds. | 05-12-2016 |
Patent application number | Description | Published |
20140347094 | RECONFIGURABLE CIRCUIT BLOCK SUPPORTING DIFFERENT INTERCONNECTION CONFIGURATIONS FOR RATE-CONVERSION CIRCUIT AND PROCESSING CIRCUIT AND RELATED METHOD THEREOF - A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration. | 11-27-2014 |
20140348264 | DIGITAL TRANSMITTER AND METHOD FOR CALIBRATING DIGITAL TRANSMITTER - A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points. | 11-27-2014 |
20140348265 | DIGITAL TRANSMITTER AND METHOD FOR COMPENSATING MISMATCH IN DIGITAL TRANSMITTER - A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal. | 11-27-2014 |
20140361913 | COMMUNICATION SYSTEM AND SAMPLE RATE CONVERTER THEREOF - A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition. | 12-11-2014 |
20150071390 | MIXER BIASING FOR INTERMODULATION DISTORTION COMPENSATION - To compensate for second-order intermodulation (IM2), it is determined whether a blocking signal is present at a receiver. A biasing differential is applied across downconverting mixers in the receiver that minimizes cross-correlation of quadrature signal components of a signal produced by the receiver in the presence of the blocking signal. | 03-12-2015 |
20160127160 | CIRCUIT, COMMUNICATION UNIT AND METHOD FOR VCO FREQUENCY ADJUSTMENT - A circuit includes a frequency generation circuit having a phase locked loop, PLL, arranged to generate a carrier frequency; and a controller operably coupled to the frequency generation circuit and arranged to determine a frequency location of one or more signals output by the frequency generation circuit and provide a control signal thereto to adjust the carrier frequency generated by the frequency generation circuit. The controller is arranged to: cooperate with the PLL to introduce a frequency offset in the generated carrier frequency in a first frequency direction; and introduce a compensating frequency offset in a baseband transmit signal in a second frequency direction opposite to the first frequency direction. | 05-05-2016 |
20160127164 | TRANSMITTER CIRCUIT, COMMUNICATION UNIT AND METHOD FOR AMPLIFYING A COMPLEX QUADRATURE SIGNAL - A transmitter circuit includes a frequency generation circuit configured to generate a local oscillator signal and a digital modulator configured to: receive data to be transmitted; quadrature modulate the received data to at least a first, Q, modulated value and a second, I, modulated value; examine the quadrature modulated data to determine if the first, Q, modulated value exceeds a limit, and in response thereto selectively modify the quadrature modulated values to a first modified, Q′, modulated value and a second modified, I′, modulated value thereby bringing only a value of the first modified, Q′, modulated value to within the limit. A local oscillator phase is selected in order to map the first modified, Q′, modulated value and second modified, I′, modulated value to desired quadrature values. A digital power amplifier, DPA, coupled to the digital quadrature modulator, is configured to amplify the quadrature modified modulated data. | 05-05-2016 |
Patent application number | Description | Published |
20120171970 | WIRELESS COMMUNICATIONS DEVICE WITH AN ADJUSTABLE IMPEDANCE MATCHING NETWORK AND ASSOCIATED METHODS - A mobile wireless communications device includes a portable housing, a transmitter carried by the portable housing and configured to modulate an input signal, and an adjustable impedance matching network coupled downstream from the transmitter. An antenna is coupled downstream from the adjustable impedance matching network, and a non-directional coupler is coupled between the adjustable impedance matching network and the antenna. A feedback receiver is coupled to the non-directional coupler to generate a feedback signal. A controller is configured to control the adjustable impedance matching network based upon the input signal and the feedback signal. | 07-05-2012 |
20120177157 | ELECTRONIC DEVICE INCLUDING VOLTAGE CONTROLLED OSCILLATOR PULLING COMPENSATION CIRCUIT AND RELATED METHODS - An electronic device includes an input configured to receive at least one baseband input signal and at least one mixer downstream from the input. The electronic device also includes a phase-locked loop (PLL) including a voltage controlled oscillator (VCO) and a phase detector coupled thereto, the VCO coupled to the at least one mixer. A power amplifier is downstream from the at least one mixer and generates at least one aggressing signal that would otherwise generate an output pull of the VCO. The electronic device also includes a VCO pulling compensation circuit coupled to the input and the VCO and configured to compensate the VCO for the output pull based upon the at least one baseband input signal and the at least one aggressing signal. | 07-12-2012 |
20120236959 | QUADRATURE COMMUNICATIONS DEVICE WITH I ANTENNAS AND Q ANTENNAS AND MODULATED POWER SUPPLY AND RELATED METHODS - A communications device may include an In-phase (I) power amplifier configured to generate an I amplified signal, a Quadrature (Q) power amplifier configured to generate a Q amplified signal, an I digital-to-analog converter (DAC) configured to generate an I signal, and a Q DAC configured to generate a Q signal. The communications device may also include an I power supply circuit coupled to the I power amplifier and to the I DAC and configured to cause the I power amplifier to modulate an I carrier signal into the I amplified signal based upon the I signal, a Q power supply circuit coupled to the Q power amplifier and to the Q DAC and configured to cause the Q power amplifier to modulate a Q carrier signal into the Q amplified signal based upon the Q signal, and at least one antenna coupled to the I and Q power amplifiers. | 09-20-2012 |
20120236960 | QUADRATURE COMMUNICATIONS DEVICE WITH I ANTENNAS AND Q ANTENNAS AND RELATED METHODS - A communications device may include In-phase (I) power amplifiers configured to respectively generate I amplified signals, Quadrature (Q) power amplifiers configured to respectively generate Q amplified signals, I antennas respectively coupled to the I power amplifiers, and Q antennas respectively coupled to the Q power amplifiers. The communications device may also include an I controller coupled to the I power amplifiers and configured to selectively enable some of the I power amplifiers, and a Q controller coupled to the Q power amplifiers and configured to selectively enable some of the Q power amplifiers. | 09-20-2012 |
20120236965 | QUADRATURE COMMUNICATIONS DEVICE WITH POWER COMBINER AND RELATED METHODS - A communications device may include In-phase (I) power amplifiers configured to generate I amplified signals, Quadrature (Q) power amplifiers configured to generate Q amplified signals, an I controller coupled to the I power amplifiers and configured to selectively enable some of the I power amplifiers, and a Q controller coupled to the Q power amplifiers and configured to selectively enable some of the Q power amplifiers. The communications device may also include a power combiner configured to combine the I amplified signals and the Q amplified signals in a combined amplified signal, and an antenna coupled to the power combiner. | 09-20-2012 |
Patent application number | Description | Published |
20130058387 | WIRELESS COMMUNICATIONS DEVICE WITH PERFORMANCE MONITORING AND ASSOCIATED METHODS - A mobile wireless communications device includes a transceiver comprising a transmitter and a receiver, an auxiliary receiver, and a controller. The transmitter is configured to upconvert a transmit baseband modulated signal and generate an RF modulated signal having a transmit impairment. The auxiliary receiver is configured to downconvert the RF modulated signal and generate a receive baseband modulated signal having the transmit impairment. The auxiliary receiver is selectively configured to operate based on a control signal in a single-mixer mode when the transmitter is selectively configured to operate in a dual-mixer mode, and in the dual-mixer mode when the transmitter is selectively configured to operate in the single-mixer mode. The controller is configured to compare the transmit baseband modulated signal to the transmit impairment to determine an error difference therebetween, and generate the control signal based on the error difference. | 03-07-2013 |
20130058388 | WIRELESS COMMUNICATIONS DEVICE WITH IMPAIRMENT COMPENSATION AND ASSOCIATED METHODS - A mobile wireless communications device includes a transceiver, an auxiliary receiver and a controller. The transceiver includes a transmitter and a receiver. The transmitter upconverts a transmit baseband modulated signal and generates an RF modulated signal having a transmit impairment. The auxiliary receiver is coupled to the transmitter and downconverts the RF modulated signal and generates a receive baseband modulated signal having a receive impairment therein spectrally separated from the transmit impairment. The controller is coupled to the transmitter and the auxiliary receiver and estimates the transmit impairment while ignoring the receive impairment based on comparing the transmit baseband modulated signal with the receive baseband modulated signal. The controller generates an impairment compensation signal based upon the estimated transmit impairment. | 03-07-2013 |
20130082853 | DIGITAL TO ANALOG CONVERTER - A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate. | 04-04-2013 |
20130095777 | METHODS AND APPARATUS FOR POWER CONTROL - Various embodiments include a method for controlling power in a transmitter, the method comprising measuring an indication of an output power of the transmitter, comparing a first value corresponding to the indication of the output power to a second value corresponding to a desired output power; and adjusting a bias of at least one component in the transmitter in order to bring the output power closer to the desired output power. Embodiments also include various methods, systems and apparatus. | 04-18-2013 |
20130165056 | WIRELESS COMMUNICATIONS DEVICE WITH AN ADJUSTABLE IMPEDANCE MATCHING NETWORK AND ASSOCIATED METHODS - A mobile wireless communications device includes a portable housing, a transmitter carried by the portable housing and configured to modulate an input signal, and an adjustable impedance matching network coupled downstream from the transmitter. An antenna is coupled downstream from the adjustable impedance matching network, and a non-directional coupler is coupled between the adjustable impedance matching network and the antenna. A feedback receiver is coupled to the non-directional coupler to generate a feedback signal. A controller is configured to control the adjustable impedance matching network based upon the input signal and the feedback signal. | 06-27-2013 |
20130176011 | DCDC CONVERTER WITH CONVERTER MODULES THAT CAN BE DYNAMICALLY ENABLED OR DISABLED - Provided is an apparatus comprising a DCDC converter having a plurality of converter modules each configured to convert current from a first voltage level to another voltage form. In accordance with an embodiment of the disclosure, the converter modules are configured to be dynamically enabled or disabled such that only each converter module that has been enabled converts current for an output of the DCDC converter. Any inefficiency that would have been introduced by converter modules that are not needed are mitigated or eliminated altogether. The effect is that efficiency can be improved during low load conditions when there is no need to enable all of the converter modules. | 07-11-2013 |
20130195152 | MOBILE WIRELESS COMMUNICATIONS DEVICE HAVING AUXILIARY RECEIVER TO DETERMINE TRANSMIT IMPAIRMENT AND GENERATE TRANSMIT IMPAIRMENT COMPENSATION SIGNAL, AND ASSOCIATED METHODS - A communications device includes a baseband input to receive a baseband signal. A transmitter is coupled to the baseband input and generates a transmit signal based upon the baseband signal, the transmit signal having an initial transmit impairment. An auxiliary receiver is coupled to the transmitter and generates a receive signal having a receive impairment therein resulting from the initial transmit impairment. A controller determines a power of the baseband signal by integrating a product of the receive signal and a complex conjugate of the baseband signal, and determines a power of the receive signal by integrating a product of the baseband signal and the receive signal. The controller also determines the initial transmit impairment based upon the power of the baseband signal and the receive signal, and generates a transmit impairment compensation signal based upon the initial transmit impairment. | 08-01-2013 |
20130196716 | COMMUNICATIONS DEVICE AND METHOD HAVING NON-TOUCH BASED INPUT SCREEN - A communications device includes a housing and a wireless transceiver and processor carried by the housing and operative with each other. An input screen is carried by the housing and comprises a plurality of spaced transceivers positioned at the input screen and connected to the processor and each configured to transmit a millimeter wave RF signal and receive reflected signals from an object positioned close to the input screen. The processor is configured to determine the location of the object relative to the input screen based on the reflected signals received at each transceiver. | 08-01-2013 |
20130196719 | MOBILE WIRELESS COMMUNICATIONS DEVICE INCLUDING SENSING TRANSISTOR AND HYSTERETIC COMPARATOR AND RELATED METHODS - A mobile wireless communications device may include a portable housing, and a supply modulator carried by the portable housing. The supply modulator may include an output node, a linear amplifier coupled to the output node, and a switching amplifier also coupled to the output node. The switching amplifier may include at least one sensing transistor configured to sense current output from the linear amplifier and generate a drive voltage, and a hysteretic comparator coupled to the at least one sensing transistor and configured to be driven by the drive voltage. The mobile wireless communications device may also include a radio frequency (RF) power amplifier coupled to the output node of the supply modulator, and a wireless transceiver carried by the portable housing and coupled to the RF power amplifier. | 08-01-2013 |
20130208770 | COMMUNICATIONS DEVICE HAVING CONTROLLER TO CORRECT AN INITIAL IQ IMBALANCE AND ASSOCIATED METHODS - A communications device includes a plurality of wireless transmitters operable at different respective frequencies and each configured to generate respective IQ signals having an initial IQ imbalance. The communications device also includes a frequency tunable auxiliary receiver, and a controller. The controller is configured to selectively couple a given wireless transmitter to the frequency tunable auxiliary receiver and tune the frequency tunable auxiliary receiver to a frequency of the given wireless transceiver, and apply predistortion to the given wireless transmitter based upon the initial IQ imbalance to reduce the initial IQ imbalance. | 08-15-2013 |
20130208827 | METHOD AND APPARATUS TO USE AUXILIARY RECEIVER TO COMPENSATE MULTIPLE TRANSMITTERS BASED UPON ONE OF THE TRANSMITTERS - A communications device includes a plurality of wireless transmitters operable at different respective frequencies and each configured to generate respective IQ signals having an initial IQ imbalance. An auxiliary receiver is coupled to a given wireless transmitter. In addition, a controller is configured to apply predistortion to the each wireless transmitter of the plurality thereof based upon the initial IQ imbalance generated by the given wireless transmitter to reduce the initial IQ imbalance in each wireless transmitter. | 08-15-2013 |
20140118081 | Multiplexed Configurable Sigma Delta Modulators for Noise Shaping in a 25-Percent Duty Cycle Digital Transmitter - A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency. | 05-01-2014 |
20140126671 | DIGITAL QUADRATURE TRANSMITTER USING GENERALIZED COORDINATES - In one embodiment, a sequence of a plurality of pairs of in-phase (I) and quadrature (Q) modulated signal samples are applied to a radio frequency digital-to-analog converter (RFDAC) for upconversion. A phase of a local oscillator (LO) signal supplied to the RFDAC is selected according to a quadrant determined by signs of a given pair of I and Q modulated signal samples. The selected phase of the LO is supplied to the RFDAC for use in upconverting the sequence of I and Q modulated signal samples. In another embodiment, a current steering DAC is used for directly upconverting the I and Q modulated signal samples. A clock signal at four times the LO frequency is supplied to a counter and to the current steering DAC. One of the I and Q modulated signal samples and negative I and negative Q modulated signal samples is selected for supply to an input of the current steering DAC based on a count state of the counter. | 05-08-2014 |
20140146917 | TRANSMITTER WITH PRE-DISTORTION MODULE, A METHOD THEREOF - Aspects of the disclosure provide a transmitter that includes a pre-distortion module and a phase controller. The pre-distortion module is configured to receive a first digital value and generate a first pre-distorted digital value based on the first digital value and a corresponding angle. The first digital value is a combination of an in-phase component and a quadrature component of a signal for transmission. The phase controller is configured to control an amplifier to drive a current according to the first pre-distorted digital value and phase information in relation to the first digital value during a first phase range of a carrier signal determined at least partially based on the angle. | 05-29-2014 |
20140219391 | HIGH DYNAMIC RANGE AMAM PREDISTORTION - A predistortion function is evaluated with in-phase (I) and quadrature (Q) data words as arguments, while additive I and Q data words are generated in accordance with a comparison of the I and Q data words with a full scale value that generates maximum current in a digital power amplifier. The additive I and Q data words are added to the computed I and Q data words to produce predistorted I and Q data words. The predistorted I and Q data words are provided in a sequence to the digital power amplifier, which generates a corresponding radio-frequency (RF) analog signal. | 08-07-2014 |
20140327473 | METHOD AND APPARATUS FOR A PROGRAMMABLE FREQUENCY DIVIDER - A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal. Iteratively selecting signals by this process results in an observed output frequency of f | 11-06-2014 |
20140362955 | ADAPTIVE IQ IMBALANCE ESTIMATION - A transceiver includes an input node to receive an input signal having in-phase (I) data and quadrature (Q) data, the input signal including several data samples. A correlation module determines an autocorrelation of the in-phase data, an autocorrelation of the quadrature data, a difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and a cross correlation between the in-phase data and the quadrature data. An averaging module determines an average of the difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and an average of the cross correlation between the in-phase data and the quadrature data, in which the averages are determined over a specified number of data samples. A compensation module, based on the average difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and the average cross correlation between the in-phase data and the quadrature data, determines compensated in-phase data and quadrature data having reduced IQ mismatch. | 12-11-2014 |
20150023451 | PREDISTORTION FACTOR DETERMINATION FOR PREDISTORTION IN POWER AMPLIFIERS - A baseband signal is generated as a sequence of complex sample values at a predetermined sample rate. A sample of the baseband signal is captured as is a sample of an output signal generated by a power amplifier from the captured sample of the baseband signal. Complex values are iteratively assigned to a complex factor intended for predistorting data such that the product of the baseband signal sample and the complex factor converges towards equivalence with the output signal sample with each iterative assignment of the complex values to the complex factor. The complex factor is stored in memory at an address associated with the value of the captured baseband signal sample. | 01-22-2015 |
20150024699 | Convergence Estimation for Iterative Predistortion Factor Determination for Predistortion in Power Amplifiers - To estimate complex factors for use in predistortion of a power amplifier, a complex factor is selected a set of complex factors a computation interval. A solution value is estimated for the selected complex factor during the computation interval by an iterative computation that constrains the estimated solution value towards a final solution value over an arbitrary number of iterations that is not bounded by the duration of the computation interval. A cumulative error in the estimated solution value is computed at each iteration over consecutive computation intervals. From the cumulative error, it is determined whether a convergence criterion is met and, if so, the estimating is terminated. The termination occurs independently of the solution value estimated for any one of the complex factors in the set. | 01-22-2015 |
Patent application number | Description | Published |
20090026492 | LATERAL JUNCTION BREAKDOWN TRIGGERED SILICON CONTROLLED RECTIFIER BASED ELECTROSTATIC DISCHARGE PROTECTION DEVICE - The components of a silicon controlled rectifier, which are a p-doped anode, an n-well middle region, a p-well middle region, and an n-doped cathode, are formed along sidewalls and a bottom surface of a shallow trench isolation structure. The p-doped anode and the n-doped cathode are formed directly underneath a top surface of a silicon substrate. A trigger mechanism that provides an instantaneous turn-on current to latch the silicon controlled rectifier to an on-state is also provided. The trigger mechanism provides a temporary surge in the voltage of the p-doped middle region, causing the instantaneous turn-on current to flow from the p-doped middle region to the n-doped cathode. Combined with the proximity of the p-doped anode to the n-doped cathode, the trigger mechanism provides a fast turn on and a short low resistance current path for the electrostatic discharge protection circuit. | 01-29-2009 |
20090231766 | ELETROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING - A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry. | 09-17-2009 |
20100181621 | SIGNAL AND POWER SUPPLY INTEGRATED ESD PROTECTION DEVICE - An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure. | 07-22-2010 |
20100246076 | Electrical Overstress Protection Circuit - A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond. | 09-30-2010 |
20100265622 | ROBUST ESD PROTECTION CIRCUIT, METHOD AND DESIGN STRUCTURE FOR TOLERANT AND FAILSAFE DESIGNS - A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event. | 10-21-2010 |
20110286135 | Silicon Controlled Rectifier Based Electrostatic Discharge Protection Circuit With Integrated JFETS, Method Of Operation And Design Structure - An enhanced turn-on time SCR based electrostatic discharge (ESD) protection circuit includes an integrated JFET, method of use and design structure. The enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit includes an integrated JFET in series with an NPN base. | 11-24-2011 |
20120043583 | LOW LEAKAGE, LOW CAPACITANCE ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECITIFER (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURE - A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction. | 02-23-2012 |
20120091530 | Low trigger voltage electrostatic discharge NFET in triple well CMOS technology - An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type. | 04-19-2012 |
20120126285 | Vertical NPNP Structure In a Triple Well CMOS Process - A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events. | 05-24-2012 |
20120250195 | ELECTROSTATIC DISCHARGE POWER CLAMP WITH A JFET BASED RC TRIGGER CIRCUIT - An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network. | 10-04-2012 |
20120305984 | SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS - An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad. | 12-06-2012 |
20130009207 | VERTICAL NPNP STRUCTURE IN A TRIPLE WELL CMOS PROCESS - A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events. | 01-10-2013 |
20130020645 | ESD FIELD-EFFECT TRANSISTOR AND INTEGRATED DIFFUSION RESISTOR - An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor. | 01-24-2013 |
20130215539 | REDUCED CURRENT LEAKAGE IN RC ESD CLAMPS - Aspects of the invention provide an electrostatic discharge (ESD) protection device with reduced current leakage, and a related method. In one embodiment, an ESD protection device for an integrated circuit (IC) is provided. The ESD protection device includes: a resistor-capacitor (RC) timing circuit for selectively turning on the ESD protection device during an ESD event; a trigger circuit for receiving an output of the RC timing circuit and generating a trigger pulse for driving at least one of: a first ESD clamp and a second ESD clamp; and a selection circuit for selecting one of: the trigger circuit or a charge pump for controlling the second ESD clamp. | 08-22-2013 |
20130293991 | CURRENT LEAKAGE IN RC ESD CLAMPS - Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation. | 11-07-2013 |
20140061803 | ELECTROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING - A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry. | 03-06-2014 |
20140339649 | FINFET TYPE DEVICE USING LDMOS - The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate. | 11-20-2014 |
20150041890 | HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION - Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate. | 02-12-2015 |
20150187753 | FIN CONTACTED ELECTROSTATIC DISCHARGE (ESD) DEVICES WITH IMPROVED HEAT DISTRIBUTION - Fin contacted electrostatic discharge (ESD) devices with improved heat distribution and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate which is aligned with at least one well region in the substrate. The method further includes forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins. The forming of the ESD device includes forming an epitaxial material spanning the two or more of the plurality of fins and forming one or more contacts on the epitaxial material. | 07-02-2015 |
20150206880 | HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION - Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate. | 07-23-2015 |
20160036219 | ESD STATE-CONTROLLED SEMICONDUCTOR-CONTROLLED RECTIFIER - Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from an electrostatic discharge event at an input/output pin. The protection circuit includes a silicon-controlled rectifier having a well and an anode in the well. The anode is coupled with the input/output pin. The protection circuit further includes a control circuit coupled with the well. The control circuit is configured to supply a first control logic voltage to the well that places the silicon-controlled rectifier in a blocking state, and a second control logic voltage to the well that places the silicon-controlled rectifier in a low impedance state. When placed in its low impedance state, the silicon-controlled rectifier is configured to divert current from the electrostatic discharge event at the input/output pin away from the integrated circuit. | 02-04-2016 |
20160141365 | GATE-ALL-AROUND FIN DEVICE - A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. | 05-19-2016 |
20160141421 | GATE-ALL-AROUND FIN DEVICE - A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. | 05-19-2016 |
Patent application number | Description | Published |
20080318905 | Prodrugs and methods of making and using the same - Prodrugs of parent drugs and methods of making and using the same are described. The prodrugs comprise an amine-containing parent drug moiety and a prodrug moiety, such as methoxyphosphonic acid or ethoxyphosphonic acid. The prodrugs may be employed in therapy for the treatment of various indications, such as pain, and in methods of decreasing the abuse potential of abuse-prone drugs and/or delaying the onset of parent drug activity and/or prolonging parent drug activity as compared to administration of a parent drug. | 12-25-2008 |
20100269858 | COMPOSITIONS AND KITS FOR THE REMOVAL OF IRRITATING COMPOUNDS FROM BODILY SURFACES - The invention provides compositions, methods and kits for the removal of harmful or irritating substances from bodily surfaces. Kits may include a composition containing capsaicin and a capsaicin-cleansing composition, e.g., a composition in which capsaicin is soluble. | 10-28-2010 |
20110184069 | METHODS AND COMPOSITIONS FOR ADMINISTRATION OF TRPV1 AGONISTS - Compositions are provided that contain a TRPV1 agonist, such as capsaicin, and a solvent system. Topical application of the composition results in rapid delivery of agonist to the dermis and epidermis. Method of using the compositions for reducing nociceptive nerve fiber function in subjects, and for treatment of capsaicin-responsive conditions are also provided. | 07-28-2011 |
20110196043 | METHODS AND COMPOSITIONS FOR ADMINISTRATION OF TRPV1 AGONISTS - Compositions are provided that contain a TRPV1 agonist, such as capsaicin, and a solvent system. Topical application of the composition results in rapid delivery of agonist to the dermis and epidermis. Method of using the compositions for reducing nociceptive nerve fiber function in subjects, and for treatment of capsaicin-responsive conditions are also provided. | 08-11-2011 |
20110212926 | WATER-SOLUBLE ACETAMINOPHEN ANALOGS - The present invention provides water-soluble acetaminophen prodrugs and formulations which may be suitable for parenteral administration. Methods of treating a disease or condition responsive to acetaminophen (such as fever and/or pain) using the acetaminophen prodrugs, as well as kits, unit dosages, and combinations with additional pharmaceutical agent(s) are also provided. | 09-01-2011 |
20110212927 | CARBONATE PRODRUGS AND METHODS OF USING THE SAME - The present invention provides carbonate prodrugs which comprise a carbonic phosphoric anhydride prodrug moiety attached to the hydroxyl or carboxyl group of a parent drug moiety. The prodrugs may provide improved physicochemical properties over the parent drug. Also provided are methods of treating a disease or condition that is responsive to the parent drug using the carbonate prodrugs, as well as kits and unit dosages. | 09-01-2011 |
20110263545 | HEPATOPROTECTANT ACETAMINOPHEN MUTUAL PRODRUGS - The present invention provides hepatoprotectant acetaminophen mutual prodrugs, which have an acetaminophen moiety covalently linked to a second moiety that may act as a hepatoprotectant against acetaminophen hepatotoxicity. Additionally, acetaminophen mutual prodrugs may have improved water solubility which may provide better suitability for parenteral and other dosage forms relative to administration of acetaminophen. Also provided are methods of treating a disease or condition that is responsive to acetaminophen (such as fever, pain and ischemic injury) using hepatoprotectant acetaminophen mutual prodrugs, as well as kits and unit dosages. | 10-27-2011 |
20120309836 | METHODS AND COMPOSITIONS FOR ADMINISTRATION OF TRPV1 AGONISTS - Compositions are provided that contain a TRPV1 agonist, such as capsaicin, and a solvent system. Topical application of the composition results in rapid delivery of agonist to the dermis and epidermis. Method of using the compositions for reducing nociceptive nerve fiber function in subjects, and for treatment of capsaicin-responsive conditions are also provided. | 12-06-2012 |
20120323258 | COMPOSITIONS AND KITS FOR THE REMOVAL OF IRRITATING COMPOUNDS FROM BODILY SURFACES - The invention provides compositions, methods and kits for the removal of harmful or irritating substances from bodily surfaces. Kits may include a composition containing capsaicin and a capsaicin-cleansing composition, e.g., a composition in which capsaicin is soluble. | 12-20-2012 |
20150073056 | METHODS AND COMPOSITIONS FOR ADMINISTRATION OF TRPV1 AGONISTS - Compositions are provided that contain a TRPV1 agonist, such as capsaicin, and a solvent system. Topical application of the composition results in rapid delivery of agonist to the dermis and epidermis. Method of using the compositions for reducing nociceptive nerve fiber function in subjects, and for treatment of capsaicin-responsive conditions are also provided. | 03-12-2015 |
20150104498 | COMPOSITIONS AND KITS FOR THE REMOVAL OF IRRITATING COMPOUNDS FROM BODILY SURFACES - The invention provides compositions, methods and kits for the removal of harmful or irritating substances from bodily surfaces. Kits may include a composition containing capsaicin and a capsaicin-cleansing composition, e.g., a composition in which capsaicin is soluble. | 04-16-2015 |
20160024126 | CARBONATE PRODRUGS AND METHODS OF USING THE SAME - The present invention provides carbonate prodrugs which comprise a carbonic phosphoric anhydride prodrug moiety attached to the hydroxyl or carboxyl group of a parent drug moiety. The prodrugs may provide improved physicochemical properties over the parent drug. Also provided are methods of treating a disease or condition that is responsive to the parent drug using the carbonate prodrugs, as well as kits and unit dosages. | 01-28-2016 |
Patent application number | Description | Published |
20090306666 | INTRAMEDULLARY NAIL WITH OBLIQUE OPENINGS - An intramedullary nail for use in a medullary canal of a long bone is provided. The nail includes a body defining a longitudinal axis of the body and an external periphery of the body for fitting in the medullary canal of the long bone. The body has a first internal wall thereof defining a first opening through the body. The first opening defines a first opening centerline. The body has a second internal wall of the body defining a second opening through the body. The second opening defines a second opening centerline. The first opening centerline and the second opening centerline are oblique with respect to each other. The longitudinal axis of the body and the first opening centerline form an acute angle between the longitudinal axis of the body and the first opening centerline. The longitudinal axis of the body and the second opening centerline forming an acute angle between the longitudinal axis of the body and the second opening centerline. | 12-10-2009 |
20120259420 | PROXIMAL TRIAL INSTRUMENT FOR USE DURING AN ORTHOPAEDIC SURGICAL PROCEDURE TO IMPLANT A REVISION HIP PROSTHESIS - A modular femoral prosthesis for use during performance of a hip revision procedure includes a proximal body component, a distal stem component, and a locking bolt. Surgical instruments and methods for use in implanting such a modular femoral prosthesis are disclosed. | 10-11-2012 |
20120259421 | VERSION-REPLICATING INSTRUMENT AND ORTHOPAEDIC SURGICAL PROCEDURE FOR USING THE SAME TO IMPLANT A REVISION HIP PROSTHESIS - A modular femoral prosthesis for use during performance of a hip revision procedure includes a proximal body component, a distal stem component, and a locking bolt. Surgical instruments and methods for use in implanting such a modular femoral prosthesis are disclosed. | 10-11-2012 |
20120259423 | ORTHOPAEDIC SURGICAL PROCEDURE FOR IMPLANTING A REVISION HIP PROSTHESIS - A modular femoral prosthesis for use during performance of a hip revision procedure includes a proximal body component, a distal stem component, and a locking bolt. Surgical instruments and methods for use in implanting such a modular femoral prosthesis are disclosed. | 10-11-2012 |
20120259424 | REVISION HIP PROSTHESIS HAVING AN IMPLANTABLE DISTAL STEM COMPONENT - A modular femoral prosthesis for use during performance of a hip revision procedure includes a proximal body component, a distal stem component, and a locking bolt. Surgical instruments and methods for use in implanting such a modular femoral prosthesis are disclosed. | 10-11-2012 |
20130218290 | REVISION HIP PROSTHESIS HAVING AN IMPLANTABLE DISTAL STEM COMPONENT - A modular femoral prosthesis for use during performance of a hip revision procedure includes a proximal body component, a distal stem component, and a locking bolt. Surgical instruments and methods for use in implanting such a modular femoral prosthesis are disclosed. | 08-22-2013 |
20140214172 | REVISION HIP PROSTHESIS HAVING AN IMPLANTABLE DISTAL STEM COMPONENT - A modular femoral prosthesis for use during performance of a hip revision procedure includes a proximal body component, a distal stem component, and a locking bolt. Surgical instruments and methods for use in implanting such a modular femoral prosthesis are disclosed. | 07-31-2014 |
20140288559 | Intramedullary Nail With Oblique Openings - An intramedullary nail for use in a medullary canal of a long bone. The nail includes a body defining a longitudinal axis and an external periphery for fitting in the medullary canal of the long bone. The body has a first internal wall thereof defining a first opening through the body, defining a first opening centerline. The body has a second internal wall defining a second opening through the body, defining a second opening centerline. The first opening centerline and the second opening centerline are oblique with respect to each other. The longitudinal axis of the body and the first opening centerline form an acute angle between the longitudinal axis of the body and the first opening centerline. The longitudinal axis of the body and the second opening centerline forming an acute angle between the longitudinal axis of the body and the second opening centerline. | 09-25-2014 |