| Patent application number | Description | Published |
|---|
| 20090003108 | SENSE AMPLIFIER METHOD AND ARRANGEMENT - In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed. | 01-01-2009 |
| 20090083495 | MEMORY CIRCUIT WITH ECC BASED WRITEBACK - Provided herein are circuits incorporating a dynamic technique to minimize power overhead with writeback. In some embodiments, error-correction-code (ECC) is used to dynamically detect bit failures and use that information to identify memory sub-sections to be enabled for writeback. | 03-26-2009 |
| 20090172283 | Reducing minimum operating voltage through hybrid cache design - Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described. | 07-02-2009 |
| 20100073994 | LEAKAGE COMPENSATION CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS - A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time. | 03-25-2010 |
| 20100082905 | DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS - Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed. | 04-01-2010 |
| 20110085389 | METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY - A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCC | 04-14-2011 |
| 20110149661 | MEMORY ARRAY HAVING EXTENDED WRITE OPERATION - In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines associated with the plurality of rows of the SRAM cells; and a selected word-line driver configured during an extended write operation to drive a selected one of the plurality of word-lines with a write word-line signal having an extended duration. Other embodiments may be described and claimed. | 06-23-2011 |
| 20110317508 | MEMORY WRITE OPERATION METHODS AND CIRCUITS - In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost. | 12-29-2011 |
