Patent application number | Description | Published |
20130185604 | FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDANT EXECUTION PIPELINES - A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions. | 07-18-2013 |
20130191432 | DYNAMIC RANGE ADJUSTING FLOATING POINT EXECUTION UNIT - A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value. | 07-25-2013 |
20140149720 | FLOATING POINT EXECUTION UNIT FOR CALCULATING PACKED SUM OF ABSOLUTE DIFFERENCES - A method and circuit arrangement provide support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost. | 05-29-2014 |
20140164464 | VECTOR EXECUTION UNIT WITH PRENORMALIZATION OF DENORMAL VALUES - A method, circuit arrangement, and program product for executing instructions including denormal values for one or more operands in a vector execution unit. A denormal value operand may be prenormalized by a first processing lane of the vector execution unit upon detecting the denormal value. The prenormalized value and any other operands of the instruction may be communicated to a dot product adder of the vector execution unit. The dot product adder performs at least a portion of the floating point operation with the prenormalized value and any other operands of the instruction. | 06-12-2014 |
20140164465 | VECTOR EXECUTION UNIT WITH PRENORMALIZATION OF DENORMAL VALUES - A method, circuit arrangement, and program product for executing instructions including denormal values for one or more operands in a vector execution unit. A denormal value operand may be prenormalized by a first processing lane of the vector execution unit upon detecting the denormal value. The prenormalized value and any other operands of the instruction may be communicated to a dot product adder of the vector execution unit. The dot product adder performs at least a portion of the floating point operation with the prenormalized value and any other operands of the instruction. | 06-12-2014 |
20140164731 | TRANSLATION MANAGEMENT INSTRUCTIONS FOR UPDATING ADDRESS TRANSLATION DATA STRUCTURES IN REMOTE PROCESSING NODES - Translation management instructions are used in a multi-node data processing system to facilitate remote management of address translation data structures distributed throughout such a system. Thus, in multi-node data processing systems where multiple processing nodes collectively handle a workload, the address translation data structures for such nodes may be collectively managed to minimize translation misses and the performance penalties typically associated therewith. | 06-12-2014 |
20140164732 | TRANSLATION MANAGEMENT INSTRUCTIONS FOR UPDATING ADDRESS TRANSLATION DATA STRUCTURES IN REMOTE PROCESSING NODES - Translation management instructions are used in a multi-node data processing system to facilitate remote management of address translation data structures distributed throughout such a system. Thus, in multi-node data processing systems where multiple processing nodes collectively handle a workload, the address translation data structures for such nodes may be collectively managed to minimize translation misses and the performance penalties typically associated therewith. | 06-12-2014 |
20140164734 | CONCURRENT MULTIPLE INSTRUCTION ISSUE OF NON-PIPELINED INSTRUCTIONS USING NON-PIPELINED OPERATION RESOURCES IN ANOTHER PROCESSING CORE - A method and circuit arrangement utilize inactive non-pipelined operation resources in one processing core of a multi-core processing unit to execute non-pipelined instructions on behalf of another processing core in the same processing unit. Adjacent processing cores in a processing unit may be coupled together such that, for example, when one processing core's non-pipelined execution sequencer is busy, that processing core may issue into another processing core's non-pipelined execution sequencer if that other processing core's non-pipelined execution sequencer is idle, thereby providing intermittent concurrent execution of multiple non-pipelined instructions within each individual processing core. | 06-12-2014 |
20140173296 | CHIP LEVEL POWER REDUCTION USING ENCODED COMMUNICATIONS - A circuit arrangement, method, and program product communicate data over a communication bus by selectively encoding data values queued for communication over the communication bus based at least in part on at least one data value queued to be communicated thereafter and at least one previously communicated encoded data value to reduce bit transitions for communication of the encoded data values. By reducing bit transitions in the data communicated over the communication bus, power consumption by the communication bus is likewise reduced. | 06-19-2014 |
20140173308 | CHIP LEVEL POWER REDUCTION USING ENCODED COMMUNICATIONS - A circuit arrangement, method, and program product communicate data over a communication bus by selectively encoding data values queued for communication over the communication bus based at least in part on at least one data value queued to be communicated thereafter and at least one previously communicated encoded data value to reduce bit transitions for communication of the encoded data values. By reducing bit transitions in the data communicated over the communication bus, power consumption by the communication bus is likewise reduced. | 06-19-2014 |
20140223143 | LOAD LATENCY SPECULATION IN AN OUT-OF-ORDER COMPUTER PROCESSOR - Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency; issuing a dependent instruction wakeup signal on an instruction wakeup bus, wherein the dependent instruction wakeup signal indicates that the load instruction will be completed upon the expiration of the expected execution latency; determining, upon the expiration of the expected execution latency, whether the load instruction has completed; and responsive to determining that the load instruction has not completed upon the expiration of the expected execution latency, issuing a negative dependent instruction wakeup signal on the instruction wakeup bus, wherein the negative dependent instruction wakeup signal indicates that the load instruction has not completed upon the expiration of the expected execution latency. | 08-07-2014 |
20140223144 | Load Latency Speculation In An Out-Of-Order Computer Processor - Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency; issuing a dependent instruction wakeup signal on an instruction wakeup bus, wherein the dependent instruction wakeup signal indicates that the load instruction will be completed upon the expiration of the expected execution latency; determining, upon the expiration of the expected execution latency, whether the load instruction has completed; and responsive to determining that the load instruction has not completed upon the expiration of the expected execution latency, issuing a negative dependent instruction wakeup signal on the instruction wakeup bus, wherein the negative dependent instruction wakeup signal indicates that the load instruction has not completed upon the expiration of the expected execution latency. | 08-07-2014 |
20150370308 | BRANCH PREDICTION WITH POWER USAGE PREDICTION AND CONTROL - A method maintains power usage prediction information for one or more functional units in branch prediction logic for a processing unit such that the power consumption of a functional unit may be selectively reduced in association with the execution of branch instructions when it is predicted that the functional unit will be idle subsequent to the execution of such branch instructions. | 12-24-2015 |
20150370557 | FLOATING POINT EXECUTION UNIT FOR CALCULATING PACKED SUM OF ABSOLUTE DIFFERENCES - A method provides support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit. Existing adders in a floating point execution unit may be utilized along with minimal additional logic in the floating point execution unit to support efficient execution of a fixed point packed sum of absolute differences instruction within the floating point execution unit, often eliminating the need for a separate vector fixed point execution unit in a processor architecture, and thereby leading to less logic and circuit area, lower power consumption and lower cost. | 12-24-2015 |
Patent application number | Description | Published |
20150026435 | INSTRUCTION SET ARCHITECTURE WITH EXTENSIBLE REGISTER ADDRESSING - A method and circuit arrangement selectively source and/or write data from/to extended registers of an extended register file based in part on whether an operand address of an instruction references a primary register of primary register file configured to store a pointer to the extended register. Control logic connected to the primary register file and the extended register file determines whether the operand address references a primary register configured to store a pointer, and responsive to the determination, the control logic causes execution logic to selectively source and/or write data from/to the extended register pointed to by the pointer stored in the referenced primary register. | 01-22-2015 |
20150026500 | GENERAL PURPOSE PROCESSING UNIT WITH LOW POWER DIGITAL SIGNAL PROCESSING (DSP) MODE - A method and circuit arrangement utilize a general purpose processing unit having a low power DSP mode for reconfiguring the general purpose processing unit to efficiently execute DSP workloads with reduced power consumption. When in a DSP mode, one or more of a data cache, an execution unit, and simultaneous multithreading may be disabled to reduce power consumption and improve performance for DSP workloads. Furthermore, partitioning of a register file to support multithreading, and register renaming functionality, may be disabled to provide an expanded set of registers for use with DSP workloads. As a result, a general purpose processing unit may be provided with enhanced performance for DSP workloads with reduced power consumption, while also not sacrificing performance for other non-DSP/general purpose workloads. | 01-22-2015 |
20150032988 | REGULAR EXPRESSION MEMORY REGION WITH INTEGRATED REGULAR EXPRESSION ENGINE - A method and circuit arrangement selectively perform regular expression matching in connection with accessing data with a processing unit based upon one or more regular expression matching-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A regular expression matching-related attribute in such a data structure may be used to control whether data being communicated between the processing unit and a communications bus is routed through an expression engine integrated with the processing unit such that regular expression matching may be performed in association with the data communication. | 01-29-2015 |
20150032999 | INSTRUCTION SET ARCHITECTURE WITH OPCODE LOOKUP USING MEMORY ATTRIBUTE - A method and circuit arrangement decode instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded. | 01-29-2015 |
20150370566 | INSTRUCTION SET ARCHITECTURE WITH OPCODE LOOKUP USING MEMORY ATTRIBUTE - A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded. | 12-24-2015 |
Patent application number | Description | Published |
20080271896 | Device in Connection with Heave Compensation - The present invention relates to a heave compensator for a riser, particularly a working riser ( | 11-06-2008 |
20110005767 | RISER SYSTEM COMPRISING PRESSURE CONTROL MEANS - The present invention regards a riser system comprising at least one riser extending from a subsea wellhead to a surface vessel, tension means for keeping the at least one riser tensioned, which tension means are connected to the vessel, a upper workover riser package (UWRP) located at the upper section of the riser and arranged to seal off the riser passage. According to the invention the UWRP is located below the connection point of the tension means to the vessel, giving the UWRP a position stationary relative a seabed, and that the UWRP comprises an interface adapted for the connection of different kinds of workover equipment. The invention also regards a method for inserting tools into a riser. | 01-13-2011 |
20150354289 | CYLINDER RELEASE ARRANGEMENT - The invention relates a cylinder release arrangement, wherein at least one cylinder is arranged with a piston within the cylinder, and a cylinder head closing off one end of the cylinder, forming a chamber between the piston and the cylinder head, wherein the cylinder is provided to arrange a leakage of fluid from one side of a piston to the other side of the piston, when the piston is in a given position within the cylinder, and release means are provided for the subsequently controlled release of the cylinder head from the cylinder. The invention also comprises a cylinder arrangement with a release mechanism. | 12-10-2015 |
Patent application number | Description | Published |
20100133046 | ELEVATOR SYSTEM, SUSPENSION ELEMENT FOR AN ELEVATOR SYSTEM, AND DEVICE FOR MANUFACTURING A SUSPENSION ELEMENT - An elevator system with a car or platform to transport passengers and/or goods as well as with a counterweight, which are arranged as traversable or movable along a travel path, and which are coupled and/or with a drive by a suspension element interrelating their motion. The suspension element is guided and/or driven by a traction sheave and/or a drive shaft and/or a deflecting pulley. The suspension element is sheathed and/or belt-type, with a first layer made of a first plasticizable and/or elastomeric material, containing a first exterior surface, and with at least one tension member—rope-type, tissue-type, or comprising a multitude of partial elements—that is embedded in the first layer of the suspension element. A manufacturing procedure for one of the suspension elements is provided. | 06-03-2010 |
20150024891 | SUSPENSION ELEMENT FOR AN ELEVATOR SYSTEM - An elevator system includes a car or platform to transport passengers and/or goods as well as a counterweight, which are arranged as traversable or movable along a travel path, and which are coupled and/or with a drive by a suspension element interrelating their motion. The suspension element is guided and/or driven by a traction sheave and/or a drive shaft and/or a deflecting pulley. The suspension element is a sheathed and/or belt-type, with a first layer made of a first plasticizable and/or elastomeric material and a second layer with a connection plane formed between the first and second layers. At least one tension member—rope-type, tissue-type, or comprising a multitude of partial elements—is embedded in an area of the connection plane, a majority of a surface of said at least one tension member directly contacting said first layer. A manufacturing procedure for one of the suspension elements is provided. | 01-22-2015 |
Patent application number | Description | Published |
20100304318 | FIRE AND WATER DISPLAY WITH INTEGRATED SAFETY FEATURES - A system for providing a combined water and fire display is provided. More specifically, a decorative display comprises a dynamic water and fire display device where fuel/air, water, and fire are integrated. The decorative display provides for unique aesthetic qualities and an appearance wherein flames are positioned at or near the surface of a volume of water. In various embodiments, the decorative display further comprises various safety features including the ability to detect and self-regulate conditions such as the existence and/or absence of a pilot flame, an adequate amount of water, and the temperature of various portions of the system. The decorative display further contemplates the ability to operate without one or more disclosed features, such as when only a water display or only a fire display is desired. | 12-02-2010 |
20140008455 | Fire and Water Display with Integrated Safety Features - A system for providing a combined water and fire display is provided. More specifically, a decorative display comprises a dynamic water and fire display device where fuel/air, water, and fire are integrated. The decorative display provides for unique aesthetic qualities and an appearance wherein flames are positioned at or near the surface of a volume of water. In various embodiments, the decorative display further comprises various safety features including the ability to detect and self-regulate conditions such as the existence and/or absence of a pilot flame, an adequate amount of water, and the temperature of various portions of the system. The decorative display further contemplates the ability to operate without one or more disclosed features, such as when only a water display or only a fire display is desired. | 01-09-2014 |