Patent application number | Description | Published |
20120281479 | Detection of Broken Word-Lines in Memory Arrays - Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective. | 11-08-2012 |
20130170301 | Wordline-to-Wordline Stress Configuration - A method and system for performing wordline-to-wordline stress routines on a storage device is disclosed. Stress routines may be performed to reduce state widening in multi-level memory cells in the storage device. However, data retention problems may result if the stress routines are performed too often. In order to perform the stress routines at the proper times, a stress control variable is used. The stress control variable may be indicative of age of the storage device (such as the number of erase cycles performed on a memory block in the storage device). The stress control variable is input to a look-up table (or other logical construct), with the output of the look-up table indicating whether to perform the wordline-to-wordline stress routine. In this way, the stress routines may be performed to reduce state widening while reducing the ill effects of data retention. | 07-04-2013 |
20130336059 | BLOCK LEVEL GRADING FOR RELIABILITY AND YIELD IMPROVEMENT - A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes. | 12-19-2013 |
20140258590 | Enhanced Dynamic Read Process with Single-Level Cell Segmentation - A dynamic read case designation is determined for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups within a computer memory. The dynamic read case designation for any given one of the multiple wordline regions specifies a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions. The number of single-level cell logic groups are folded into a multi-level cell block. The folding includes reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation, as determined for the wordline region within which the read memory cells reside. | 09-11-2014 |
20140269071 | PRESERVING DATA FROM ADJACENT WORD LINES WHILE PROGRAMMING BINARY NON-VOLATILE STORAGE ELEMENTS - A system and methods for programming non-volatile memory elements by using latches to transfer data. Upon discovering errors in previously programmed non-volatile memory elements, the system recovers the corresponding data from the latches and programming the recovered data to other non-volatile memory elements. | 09-18-2014 |
20150100851 | ADAPTIVE EPWR (ENHANCED POST WRITE READ) SCHEDULING - A system and method for adaptive enhanced post write reads (EPWRs) is provided. An error rate of a block of solid state memory may be determined. Foldings may be performed more times between two consecutive enhanced post write reads on the block when the determined error rate of the block is a lower value than when the determined error rate is a higher value. The foldings may be performed by folding data into the block of the solid state memory. | 04-09-2015 |
20150149693 | Targeted Copy of Data Relocation - In a nonvolatile memory array that has a binary cache formed of SLC blocks and a main memory formed of MLC blocks, corrupted data along an MLC word line is corrected and relocated, along with any other data along the MLC word line, to binary cache, before it becomes uncorrectable. Subsequent reads of the relocated data directed to binary cache. | 05-28-2015 |
20150301754 | Storage Module and Method for Configuring the Storage Module with Memory Operation Parameters - A storage module and method for configuring the storage module with memory operation parameters are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a selection of one of a plurality of sets of memory operation parameters stored in the storage module and perform at least one of a read operation and a write operation on the memory in accordance with the selected set of memory operation parameters. | 10-22-2015 |