Patent application number | Description | Published |
20080238503 | Injection locked LC VCO clock deskewing - In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock. | 10-02-2008 |
20090086871 | Apparatus for distributing a signal - An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal. | 04-02-2009 |
20090289700 | FORWARDED CLOCK FILTERING - Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed. | 11-26-2009 |
20120281323 | INTEGRATED CIRCUIT PASSIVE SIGNAL DISTRIBUTION - For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed. | 11-08-2012 |
20140203798 | ON-DIE ALL-DIGITAL DELAY MEASUREMENT CIRCUIT - An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks. | 07-24-2014 |
Patent application number | Description | Published |
20110161748 | Systems, methods, and apparatuses for hybrid memory - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 06-30-2011 |
20120284436 | SYSTEMS, METHODS, AND APPARATUSES FOR HYBRID MEMORY - Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer. | 11-08-2012 |