Morrie
Morrie Altmejd, Toronto CA
Patent application number | Description | Published |
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20100109739 | ACTIVE GUARDING FOR REDUCTION OF RESISTIVE AND CAPACITIVE SIGNAL LOADING WITH ADJUSTABLE CONTROL OF COMPENSATION LEVEL - In various embodiments, applicants' teachings are related to an active guarding circuit and method for reducing parasitic impedance signal loading on a signal-transmission channel that is shunted by a parasitic impedance. The presence of an electrical signal on the signal-transmission channel causes a leakage current to flow through the parasitic impedance. In various embodiments, the circuit comprises an amplifier and an impedance, one terminal of the impedance is coupled to the signal-transmission channel. The input of the amplifier is coupled to the signal-transmission channel and the output is coupled to the other terminal of the impedance so as to cause a compensation current to flow through the impedance. The gain of the amplifier and the value of the impedance are selected so that the compensation current has a magnitude substantially equal to the leakage current magnitude. | 05-06-2010 |
Morrie Berglas, Ontario CA
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20090063824 | Compound instructions in a multi-threaded processor - A multi-threaded processor determines which threads to execute, switches between execution of threads in dependence on the determination, each thread being coupled to a respective register for storing the state of the thread and used in executing instructions on the thread and includes a further register shared by all the threads. The executing threads use the further register to improve execution performance and prevents the switching of execution to another thread while the internal register is in use. | 03-05-2009 |
Morrie Berglas, London GB
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20080244247 | Processing long-latency instructions in a pipelined processor - There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed. The method comprises the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time. The processor includes means for performing steps a), b) and c) of the method. | 10-02-2008 |
20120246451 | PROCESSING LONG-LATENCY INSTRUCTIONS IN A PIPELINED PROCESSOR - There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed. The method comprises the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time. The processor includes means for performing steps a), b) and c) of the method. | 09-27-2012 |
Morrie Berglas, Kings Langley GB
Patent application number | Description | Published |
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20130113792 | Three Dimensional Computer Graphics System - A blend buffer has a pre-determined plurality of locations, each with a set of registers. The locations are allocatable to pixels. The blend buffer has a first write port and a second write port. The first write port couples with a texture read unit and the second write port couples with a blending unit. The blending unit also interfaces with a read port of the blend buffer. The texture unit receives texture coordinates from a texture coordinate calculator. The blending unit is operable to interface with the texture coordinate calculator. The blending unit is operable to perform write only transactions of pixel data to locations of a render target that corresponds to respective locations in the blend buffer, once after completion of processing the pixels for which data is being written. | 05-09-2013 |