| Patent application number | Description | Published |
|---|
| 20090100211 | Verification-scenario generating apparatus, verification-scenario generating method, and computer product - Hardware blocks respectively of an arbitrary access origin and an arbitrary access destination that are mutually accessible are extracted from among a plurality of hardware blocks constituting a bus system to be verified, and a path reaching from the access-origin hardware block to the access-destination hardware block is searched for. For each path found, a verification scenario is generated to verify transactions of the access-origin hardware block for a case where access to an address range assigned to the access-destination hardware block occurs, and the verification scenario is output being correlated with the path that corresponds thereto. | 04-16-2009 |
| 20090259610 | VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT - A verification support apparatus includes an identifying unit that, by using a pre-change specification and a post-change specification given before and after a specification change in a subject to be verified, identifies an area that has changed from among a plurality of specification items included in the post-change specification and a selecting unit that selects a specification item from among the areas identified by the identifying unit. The verification support apparatus further includes a searching unit that, by referring a transition graph concerning the specification items included in the post-change specification and by tracing specification items as origins of transitions from a starting point that is the specification item selected by the selecting unit, searches for a route made up of specification items affected by the specification change; and an output unit that outputs a search result of the searching unit. | 10-15-2009 |
| 20090276740 | VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT - In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output. | 11-05-2009 |
| 20100058262 | VERIFICATION ASSISTING PROGRAM, VERIFICATION ASSISTING APPARATUS, AND VERIFICATION ASSISTING METHOD - A verification assisting apparatus for assisting a matching check between a specification and implementation of an object includes: an obtaining unit that obtains a specification description including elements executed to realize functions of the object and restricting conditions of the elements to realize the functions, and an implementation description concerning the functions; a creating unit that creates a graph structure including, as nodes, the elements and the restricting conditions, based on the implementation description; a first correlating unit that correlates nodes in the graph structure with the implementation description; a second correlating unit that correlates a node in the graph structure with the specification description, by detecting the node in the structure using a description concerning the element or the restricting condition in the specification description; and an outputting unit that outputs the correlation results. | 03-04-2010 |
| 20110046938 | Verification apparatus and design verification program - A design verification apparatus includes a dataset generator to generate verification datasets which associate each unit process of a plurality of procedures (processing scenarios) described in a design specification of a target product with an identifier (label) designating which portion of the design specification is to be verified. A process priority setting unit assigns a process priority to each verification dataset according to specified identifiers. An output processor outputs data identifying the verification datasets, together with explicit indication of their process priorities. | 02-24-2011 |
| 20110061035 | VERFICATION APPARATUS AND DESIGN VERFICATION PROGRAM - In a design verification apparatus, a priority resolver selects one or more verification datasets for verifying a procedure described in a design specification of a target product, in response to a verification request for that procedure. The priority resolver determines a priority score of each parameter that the selected verification datasets specify as a constraint on the procedure. A verification order resolver determines a verification order of the selected verification datasets, based on the priority scores determined by the priority resolver. An output processor produces data identifying the verification datasets, together with indication of the determined verification order. | 03-10-2011 |
| 20110138228 | VERIFICATION COMPUTER PRODUCT AND APPARATUS - A non-transitory, computer-readable recording medium stores therein a verification program that causes a computer to execute detecting from a structure expressing a group of scenarios for verifying an operation of a design under verification and by hierarchizing sequences for realizing the operation as nodes, a similar node similar to a faulty node representing a sequence in which a fault has occurred; generating a string of sequences represented by a group of nodes on a path starting from a start node of the structure to the detected similar node; and outputting the generated string of sequences. | 06-09-2011 |
