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Moriyoshi

Moriyoshi Awasaka, Shioya-Gun JP

Patent application numberDescriptionPublished
20120074344FLUID PASSAGE VALVE - A fluid passage valve is equipped with a valve body which is disposed rotatably through first and second shafts, a movable seat having a communication hole therein, and an elastic member that urges the movable seat toward a side opposite from the valve body. The first and second shafts are assembled and installed on the valve body such that an axis thereof is disposed at a position offset from a center of curvature of a spherical surface portion of the valve body. The fluid passage valve is placed in a valve-closed condition by the spherical surface portion abutting against a seating surface and closing the communication hole, and is placed in an open condition by the valve body separating away from the movable seat and thereby opening the communication hole.03-29-2012

Moriyoshi Nakashima, Amagasaki-Shi JP

Patent application numberDescriptionPublished
20080265433INTERPOSER, SEMICONDUCTOR CHIP MOUNTED SUB-BOARD, AND SEMICONDUCTOR PACKAGE - A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.10-30-2008
20090065922SEMICONDUCTOR DEVICE PACKAGE STRUCTURE - A semiconductor chip mounted interposer (03-12-2009

Moriyoshi Ohara, Kanagawa JP

Patent application numberDescriptionPublished
20100325361METHOD FOR CONTROLLING CACHE - A computer-implemented method, apparatus, and computer program-product for controlling cache. The method includes the steps of assigning a value corresponding to a transaction to a memory object that is created while a computer application is processing the transaction; adding the assigned value as a transaction flag value to a flag area of a cache array in accordance with the storage of the memory object in the cache; registering the corresponding transaction flag value as a victim candidate at the completion of the transaction; and in response to eviction of a cache line, preferentially evicting a cache line having the transaction flag value registered as the victim candidate.12-23-2010

Moriyoshi Ohara, Yokohama-Shi JP

Patent applications by Moriyoshi Ohara, Yokohama-Shi JP

Moriyoshi Ohara, Kanagawa-Ken JP

Patent application numberDescriptionPublished
20080238734Fast Implementation Of Decoding Function For Variable Length Encoding - An embodiment of the present inventions is a method for encoding/decoding data of variable length format and is used to omit unnecessary pieces of data for the purpose of improving processing performance, reducing the size of data on communication paths and efficiently using limited physical memory. As examples of such variable length encoding, BER compression and UTF-8 encoding of UNICODE text, etc., are cited. While the amount of data can be reduced through encoding, before the data is actually used, it is necessary to restore (decode) it to the original data, which requires a great deal of processing time. One aspect of the present invention is improving decoding by reducing the processing time required to decode the encoded data.10-02-2008
20080238735Fast Implementation Of Decoding Function For Variable Length Encoding - An embodiment of the present inventions is a method for encoding/decoding data of variable length format and is used to omit unnecessary pieces of data for the purpose of improving processing performance, reducing the size of data on communication paths and efficiently using limited physical memory. As examples of such variable length encoding, BER compression and UTF-8 encoding of UNICODE text, etc., are cited. While the amount of data can be reduced through encoding, before the data is actually used, it is necessary to restore (decode) it to the original data, which requires a great deal of processing time. One aspect of the present invention is improving decoding by reducing the processing time required to decode the encoded data.10-02-2008
20080270772Reduced data transfer during processor context switching - Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.10-30-2008
20090222644Merge Operations of Data Arrays Based on SIMD Instructions - A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge OR operations.09-03-2009

Patent applications by Moriyoshi Ohara, Kanagawa-Ken JP