Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees

Morein

Bror Morein, Uppsala SE

Patent application number	Description	Published
20090208562	Vaccine Composition Comprising a Fibronectin Binding Protein or a Fibronectin Binding Peptide - The present invention relates to a composition comprising at least one fibronectin binding protein, and/or at least one a truncated fibronectin binding protein and/or at least one fibronectin binding peptide, all comprising at least one fibronectin binding domain; and at least one Iscom matrixcomplex and/or liposome and/or at least one lipid and at least one saponin, whereby the at least one lipid and the at least one saponin may be in complex, solution or suspension. Further, it regards use thereof for the production of a vaccine against a micro organism that comprises at least one one fibronectin binding domain. It also regards a kit of parts comprising at least two compartments, wherein one compartment comprises at least one truncated fibronectin binding protein and/or a fibronectin binding peptide, that comprises at least one fibronectin binding domain, and another compartment comprises an instruction for use and/or an Iscom matrixcomplex and/or an iscom complex and or a liposome. Further it relates to a method for vaccination of an individual.	08-20-2009
20100119591	USE OF LIPID CONTAINING PARTICLES COMPRISING QUILLAJA SAPONINS FOR THE TREATMENT OF CANCER - The present invention relates to the use of lipid containing particles, such as liposomes, iscom and/or iscom matrix and posintros, comprising at least one lipid and at least one saponin for the preparation of a pharmaceutical for the treatment of cancer. The saponins are preferably from	05-13-2010
20110081378	COMPOSITION COMPRISING ISCOM PARTICLES AND LIVE MICRO-ORGANISMS - Iscom particles can be used as an adjuvant for preparing of an antigenic composition which comprises live micro-organisms and/or killed micro-organisms and/or antigenic molecules. A composition may comprise at least one iscom particle and one or more live micro-organisms and/or killed micro-organisms and/or antigenic molecules. A kit can comprise at least one compartment containing at least one living organism and at least one compartment containing at least one iscom particle.	04-07-2011
20110104197	METHOD AND A FILTER FOR CAPTURING AIRBORNE AGENTS - A method for capturing airborne agents or products of agents, such as microorganisms, including viruses, and microbial antigens, toxins and allergens, comprising the formation of at least one curtain of charged particles in the form of an emulsion, a suspension or an aerosol, constantly renewing and regenerating said at least one curtain, and passing air containing airborne agents through said at least one curtain, which acting as a filter captures said agents; as well as a particle formulation for performing the method, comprising any charged particles dispersed in a liquid, including lipid-containing particles, e.g. in the form of an emulsion, or micelles, or lipid-containing particles in the form of an aerosol, or any other charged airborne particles in an aerosol.	05-05-2011

Stephen Morein, San Jose, CA US

Patent application number	Description	Published
20090125747	Asymmetrical IO Method and System - An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.	05-14-2009
20090248941	Peer-To-Peer Special Purpose Processor Architecture and Method - A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.	10-01-2009
20100088452	Internal BUS Bridge Architecture and Method in Multi-Processor Systems - An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.	04-08-2010
20100088453	Multi-Processor Architecture and Method - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.	04-08-2010

Stephen L. Morein, San Jose, CA US

Patent application number	Description	Published
20090086563	Memory Word Line Driver Featuring Reduced Power Consumption - Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line goes high and the rest remain zero. The decoder circuit comprises two PMOS transistors in series with an NMOS-based inverter circuit. This arrangement reduces the leakage current through the NMOS transistor when the word line is not selected. An array of word line drivers incorporating a NOR-based decoder includes a shared pull up PMOS transistor for one of two address lines. The shared pull-up PMOS transistor is manufactured to a size on the order of at least two times the width of the remaining transistors of each word line stage.	04-02-2009
20090089632	Memory Sense Scan Circuit And Test Interface - Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.	04-02-2009

William G. Morein, Seattle, WA US

Patent application number	Description	Published
20090199081	WEB-BASED VISUALIZATION, REFRESH, AND CONSUMPTION OF DATA-LINKED DIAGRAMS - Technologies are described herein for refreshing data-linked diagrams on a server computer and viewing and consuming the refreshed diagrams via a Web browser. A drawing program allows equations within a diagram definition to define how external data is utilized to modify the attributes of a diagram element. When the diagram is published to a server computer, the definition is converted to server-legible definition. A published diagram is generated that includes a diagram representation defined by the server-legible definition. Upon a request for the published diagram, the external data is refreshed and the diagram definition is updated. The equations are recalculated to generate new element attributes. The diagram representation is then updated with the new attributes and returned for display by a client Web browser. An interface provides exploration tools and a client API exposes methods for surfacing external data and annotating the diagram.	08-06-2009

William Guthrie Morein, Seattle, WA US

Patent application number	Description	Published
20090195553	SERVER-BASED RASTERIZATION OF VECTOR GRAPHICS - Technologies are described herein for high-performance rasterization of a vector graphic on a server computer. A vector graphic loader receives the vector graphic and generates an intermediate data structure from the vector graphic. A vector graphic renderer receives the intermediate data structure and renders the intermediate data structure to a render surface. An imaging component encodes the contents of the render surface to a raster image in a standard image format. The vector graphic loader and the vector graphic renderer are configured for multi-threaded and multi-processor execution on a server computer, which provides high performance.	08-06-2009