Patent application number | Description | Published |
20090048337 | Modulation of anxiety through blockade of anandamide hydrolysis - Fatty acid amide hydrolase inhibitors of the Formula: | 02-19-2009 |
20090082435 | Methods, Compositions, And Compounds For Modulation Of Monoacylglycerol Lipase, Pain, And Stress-Related Disorders - Methods, compositions, and compounds for inhibiting monoacyglycerol lipase, and for treating pain, for modulating stress-induced analgesia or for treating stress-induced disorders in mammals are provided. | 03-26-2009 |
20100267836 | NOVEL MELATONIN LIGANDS HAVING ANTIDEPRESSANT ACTIVITY AS WELL AS SLEEP INDUCING PROPERTIES - Novel melatonin ligands of Formula I: | 10-21-2010 |
20120010283 | MODULATION OF ANXIETY THROUGH BLOCKADE OF ANANDAMIDE HYDROLYSIS - Fatty acid amide hydrolase inhibitors of the Formula: | 01-12-2012 |
20130217764 | PERIPHERALLY RESTRICTED FAAH INHIBITORS - Peripherally restricted inhibitors of fatty acid amide hydrolase (FAAH) are provided. The compounds can suppress FAAH activity and increases anandamide levels outside the central nervous system (CNS). Despite their relative inability to access brain and spinal cord, the compounds attenuate behavioral responses indicative of persistent pain in rodent models of inflammation and peripheral nerve injury, and suppresses noxious stimulus-evoked neuronal activation in spinal cord regions implicated in nociceptive processing. CBi receptor blockade prevents these effects. Accordingly, the invention also provides methods, and pharmaceutical compositions for treating conditions in which the inhibition of peripheral FAAH would be of benefit. The compounds of the invention are according to the formula (I): in which R | 08-22-2013 |
20130281490 | Disubstituted Beta-lactones as Inhibitors of N-Acylethanolamine Acid Amidase (NAAA) - The present invention provides compounds and pharmaceutical compositions for inhibiting N-acylethanolamine acid amidase (NAAA). Inhibition of NAAA is contemplated as a method to sustain the levels of palmitoylethanolamide (PEA) and oleylethanolamide (OEA), two substrates of NAAA, in conditions characterized by reduced concentrations of PEA and OEA. The invention also provides methods for treating inflammatory diseases and pain, and other disorders in which decreased levels of PEA and OEA are associated with the disorder. | 10-24-2013 |
20140094508 | COMPOSITIONS AND METHODS OF INHIBITING N-ACYLETHANOLAMINE-HYDROLYZING ACID AMIDASE - Compounds and pharmaceutical compositions are contemplated that inhibit N-acyl-ethanolamine-hydrolyzing acid amidase (NAAA) to so increase the concentration of the substrate of NAAA, palmitoylethanolamide (PEA). NAAA inhibition is contemplated to be effective to alleviate conditions associated with a reduced concentration of PEA. Among other uses, various NAAA inhibitors are especially contemplated as therapeutic agents in the treatment of inflammatory diseases. | 04-03-2014 |
20140288170 | META-SUBSTITUTED BIPHENYL PERIPHERALLY RESTRICTED FAAH INHIBITORS - The present invention provides methods of making and using peripherally restricted inhibitors of fatty acid amide hydrolase (FAAH). The present invention provides compounds and compositions that suppress FAAH activity and increases anandamide levels outside the central nervous system (CNS). The present invention also sets forth methods for inhibiting FAAH as well as methods for treating conditions such as, but not limited to, pain, inflammation, immune disorders, dermatitis, mucositis, the over reactivity of peripheral sensory neurons, neurodermatitis, and an overactive bladder. Accordingly, the invention also provides compounds, methods, and pharmaceutical compositions for treating conditions in which the selective inhibition of peripheral FAAH (as opposed to CNS FAAH) would be of benefit. | 09-25-2014 |
20150045442 | NOVEL MELATONIN LIGANDS HAVING ANTIDEPRESSANT ACTIVITY AS WELL AS SLEEP INDUCING PROPERTIES - Novel melatonin ligands of Formula I: | 02-12-2015 |
20150111892 | ACID CERAMIDASE INHIBITORS AND THEIR USE AS MEDICAMENTS - The present invention concerns, in a first aspect, compounds of Formula I as defined herein, pharmaceutically acceptable salts thereof and pharmaceutical compositions containing such compounds. The present invention also relates to compounds of Formula I for use as acid ceramidase inhibitors, and in the treatment of cancer and other disorders in which modulation of the levels of ceramide is clinically relevant. | 04-23-2015 |
Patent application number | Description | Published |
20100022061 | Spacer Shape Engineering for Void-Free Gap-Filling Process - A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer. | 01-28-2010 |
20120025329 | Spacer Shape Engineering for Void-Free Gap-Filling Process - A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer. | 02-02-2012 |
20130181300 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 07-18-2013 |
20130187206 | FinFETs and Methods for Forming the Same - A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions. | 07-25-2013 |
20130228876 | FinFET Design with LDD Extensions - System and method for forming lightly doped drain (LDD) extensions. An embodiment comprises forming a gate electrode on a semiconductor fin and forming a dielectric layer over the gate electrode. The gate electrode is then etched to expose a portion of the semiconductor fin. The exposed portions of the fin comprise the LDD extensions. | 09-05-2013 |
20140103453 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 04-17-2014 |
20150155208 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 06-04-2015 |
Patent application number | Description | Published |
20100038721 | METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function. | 02-18-2010 |
20100041223 | METHOD OF INTEGRATING HIGH-K/METAL GATE IN CMOS PROCESS FLOW - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function. | 02-18-2010 |
20100048013 | NOVEL HIGH-K METAL GATE CMOS PATTERNING METHOD - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function. | 02-25-2010 |
20110275212 | Integrated High-K/Metal Gate in CMOS Process Flow - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench. | 11-10-2011 |
20130140643 | INTEGRATED HIGH-K/METAL GATE IN CMOS PROCESS FLOW - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench. | 06-06-2013 |
20130207265 | STRUCTURE AND METHOD OF MAKING THE SAME - A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width. | 08-15-2013 |
20140001566 | Method Of Forming A Single Metal That Performs N Work Function And P Work Function In A High-K/Metal Gate Process | 01-02-2014 |
20150037976 | METHOD OF MAKING A STRUCTURE - A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width. | 02-05-2015 |
20150061031 | Integrated High-K/Metal Gate In CMOS Process Flow - A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region. | 03-05-2015 |