| Patent application number | Description | Published |
|---|
| 20090051417 | Voltage Supply Insensitive Bias Circuits - A voltage-insensitive circuit includes a second circuit, and a biasing means for providing a constant bias current to the second circuit, the bias current being insensitive to power fluctuations of the voltage-insensitive circuit. | 02-26-2009 |
| 20090309656 | MULTIPLE OUTPUT POWER MODE AMPLIFIER - A multi-mode power amplifier and an electronic device including the amplifier are described. | 12-17-2009 |
| 20100327969 | POWER AMPLIFIER HAVING PARALLEL AMPLIFICATION STAGES AND ASSOCIATED IMPEDANCE MATCHING NETWORKS - An amplification device includes a series combination of a driver stage, an output terminal matching network, and a secondary amplification stage. The driver stage includes a driver amplifier and an output matching network. The secondary amplification stage includes a parallel combination of an impedance transformation network and a main amplification stage. The main amplification stage includes a plurality of main amplification branches in parallel with each other, and an input matching network in series with the parallel combination. Each main amplification branch includes a main amplifier, and input and output impedance matching networks. A control circuit supplies activation signals to the main amplification branches to selectively turn them on and off. The device has no switches in the path of the signal that is amplified. In at least one operating mode, the control circuit turns on at least two of the main amplification branches at the same time. | 12-30-2010 |
| 20120013401 | POWER AMPLIFIER WITH SELECTABLE LOAD IMPEDANCE AND METHOD OF AMPLIFYING A SIGNAL WITH SELECTABLE LOAD IMPEDANCE - A device includes: a power amplifier, including a supply voltage terminal, an input port and an output port, and the power amplifier being configured to receive a supply voltage at the supply voltage terminal, an input signal through the input port, to amplify the received input signal, and to output an amplified output signal through the output port; a variable impedance matching circuit having an input terminal connected to the output port of the power amplifier, and having an output terminal for being connected to a load; and a controller including a voltage measuring unit configured to measure the supply voltage, to compare the measured supply voltage with a threshold voltage, and to control the variable impedance matching circuit based on a result of the comparison so as to adjust a load impedance seen by the power amplifier at its output port. | 01-19-2012 |
| Patent application number | Description | Published |
|---|
| 20110143821 | POWER AMPLIFICATION MODULE FOR MOBILE COMMUNICATION TERMINAL - Disclosed herein is a power amplification module for a mobile communication terminal. The power amplification module includes a balanced power amplifier configured to divide an input signal using a phase difference, amplify resulting signals, and combine the amplified signals with each other, and a transmission power detection unit connected to an isolation terminal formed on an output side of the balanced power amplifier and configured to amplify a micro-power signal, which is transmitted to the isolation terminal from an outside of the transmission power detection unit, and to transmit the amplified signal. Accordingly, since the detection signal to input terminal and detection signal output terminal of a transmission power detection unit can be easily implemented using an internal circuit, the entire size of the power amplification module can be reduced. Further, characteristic of isolation between the detection signal input terminal and the detection signal output terminal can be improved. | 06-16-2011 |
| 20110156817 | POWER AMPLIFIER - Disclosed herein is a power amplifier. The power amplifier includes a first common source transistor for amplifying an input signal into a predetermined level, a second common source transistor for compensating for input capacitance and performing auxiliary amplification for the first common source transistor, and a common gate transistor connected to the first common source transistor in a cascode structure, configured to be connected in parallel to the second common source transistor and prevent the first common source transistor from breaking down, and configured to output a signal amplified by a value obtained by adding the gain of the first common source transistor and the gain of the second common source transistor to each other. | 06-30-2011 |
