| Patent application number | Description | Published |
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| 20080231499 | LOCATION TRACKING OF MOBILE PHONE USING GPS FUNCTION - A system, method, service and mobile device are disclosed for providing a location of the mobile device. The invention utilizes a mobile phone with a global positioning system (GPS) module which is located in a wireless network. A third party device is able to submit a location query to a mobile telephone service operator (MTSO). This location query includes the mobile phone's telephone number. Using the telephone number, the MTSO determines the base station with which the mobile phone is associated. The location query is then forwarded to the mobile phone via the base station. The mobile phone collects the GPS data from the GPS module and forwards the GPS data to the base station. The base station converts the GPS data to location information and forwards the location information to the third party device via the MTSO. | 09-25-2008 |
| 20080259086 | HYBRID IMAGE PROCESSING SYSTEM - The present invention provides a hybrid image processing system, which generally includes an image processing unit for receiving image data corresponding to a set of images, generating commands for processing the image data, and sending the images and the commands to an image processing unit of the hybrid image processing system. Upon receipt, the image processing unit will recognize and interpret the commands, assign and/or schedule tasks for processing the image data to a set of (e.g., special) processing engines based on the commands, and return results and/or processed image data to the image interface unit. | 10-23-2008 |
| 20080260296 | HETEROGENEOUS IMAGE PROCESSING SYSTEM - The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion. | 10-23-2008 |
| 20080260297 | HETEROGENEOUS IMAGE PROCESSING SYSTEM - The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a hybrid computing system. To this extent, a hybrid system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications on a hybrid image processing system referred to herein as an image co-processor that comprises (among other things) a plurality of special purpose engines (SPEs) that work to process multiple images in an accelerated fashion. | 10-23-2008 |
| 20090002151 | WIRELESS SENSOR NETWORK - A system and method for implementing a wireless sensor network. The system comprises a plurality of motes, each mote having a sensor and a wireless communication system for communicating with neighboring motes; a distributed routing table distributed amongst each of the plurality of motes; and an update system for periodically updating the distributed routing table. | 01-01-2009 |
| 20090060157 | CONFERENCE CALL PRIORITIZATION - An improved solution for prioritizing conference call participants is provided. In an embodiment of the invention, a method includes detecting a sound of a first conference call participant; disabling a distribution of a sound of a second conference call participant upon the detecting; and enabling the distribution of the sound of the second conference call participant after an expiration of a time period. In an embodiment, a higher priority may be assigned to a specific participant, such as the host, an administrator, or manager. | 03-05-2009 |
| 20090110326 | HIGH BANDWIDTH IMAGE PROCESSING SYSTEM - The present invention provides a high bandwidth image processing system, which generally includes an image processing unit having a set of servers that each have a universal operating system for receiving image data corresponding to a set of images, generating commands for processing the image data, and sending the images and the commands to an image processing unit (also having a universal operating system(s)) of the high bandwidth image processing system. Upon receipt, the image processing unit will recognize and interpret the commands, assign and/or schedule tasks for processing the image data to a set of (e.g., special) processing engines based on the commands, and return results and/or processed image data to the image interface unit. | 04-30-2009 |
| 20090132082 | STRIPED ON-CHIP INDUCTOR - Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters. | 05-21-2009 |
| 20090132582 | PROCESSOR-SERVER HYBRID SYSTEM FOR PROCESSING DATA - The present invention relates to a processor-server hybrid system that comprises (among other things) a set (one or more of servers (e.g., mainframes) and a set of front-end application optimized processors. Moreover, implementations of the invention provide a server and processor hybrid system and method for distributing and managing the execution of applications at a fine-grained level via an I/O-connected hybrid system. This method allows one system to be used to manage and control the system functions, and one or more other systems to co-processor. | 05-21-2009 |
| 20090132638 | SERVER-PROCESSOR HYBRID SYSTEM FOR PROCESSING DATA - The present invention relates to a server-processor hybrid system that comprises (among other things) a set (one or more) of front-end servers (e.g., mainframes) and a set of back-end application optimized processors. Moreover, implementations of the invention provide a server and processor hybrid system and method for distributing and managing the execution of applications at a fine-grained level via an I/O-connected hybrid system. This method allows one system to be used to manage and control the system functions, and one or more other systems to co-processor. | 05-21-2009 |
| 20090134844 | APPARATUS AND METHOD FOR RECYCLING AND REUSING CHARGE IN AN ELECTRONIC CIRCUIT - An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system. | 05-28-2009 |
| 20090138737 | APPARATUS, METHOD AND PROGRAM PRODUCT FOR ADAPTIVE REAL-TIME POWER AND PERFOMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS - An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized. | 05-28-2009 |
| 20090138748 | APPARATUS AND METHOD FOR MICRO PERFORMANCE TUNING OF A CLOCKED DIGITAL SYSTEM - An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency. | 05-28-2009 |
| 20090150555 | MEMORY TO MEMORY COMMUNICATION AND STORAGE FOR HYBRID SYSTEMS - The present invention relates to memory to memory communication and storage for hybrid systems. Under the present invention, a data stream is received on a first computing device of a hybrid system. An attempt is made to store the data stream on the first computing device up to a per stream limit and a total storage limit of the first computing device. It is then determined whether to store at least a portion of the data stream on a second computing device of the hybrid system that is in communication with the first computing device. This decision is based on the per stream limit and the total storage limit of the first computing device as well as a per stream limit and a total storage limit of the second computing device. Thereafter, the at least a portion of the data stream and a control signal are communicated to the second computing device for storage. | 06-11-2009 |
| 20090150556 | MEMORY TO STORAGE COMMUNICATION FOR HYBRID SYSTEMS - Under the present invention, a hybrid system having multiple computing devices and storage devices is provided. The “multiple computing devices” typically include at least one server and at least one processor, both of which include local memory. Thus, the hybrid system will typically have at least two different types of computing devices. The “multiple storage devices” are typically implemented within a storage area network, and include at least one staging storage device and at least one processed data storage device. These devices will be utilized to store incoming data streams in the event that either computing device lacks sufficient space and/or sufficient credits for transmission to another computing device. | 06-11-2009 |
| 20090152612 | HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN - A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance. | 06-18-2009 |
| 20090190601 | VIRTUAL WEB SERVICE - An improved solution for Web services is provided. In an embodiment of the invention, a method for providing a virtual Web service includes: providing a Web service gatekeeper, where the gatekeeper acts as an access point to multiple private internal enterprise environments; and then the gatekeeper receives a request for access to one, or more, of these private internal enterprise environments. | 07-30-2009 |
| 20090202060 | TELEPHONIC VOICE AUTHENTICATION AND DISPLAY - An improved solution for telephonic voice authentication and display is provided. A method of identifying conference call participants includes detecting a sound made by one of conference call participants; identifying this conference call participant based on the sound; and then displaying an attribute of the conference call participant to one of the other conference call participants. The attribute may include a picture, a name, and/or other information related to the identified conference call participant. | 08-13-2009 |
| 20090202149 | PRE-PROCESSING OPTIMIZATION OF AN IMAGE PROCESSING SYSTEM - The present approach increases bandwidth by performing at least two functions at the pre-processing level. Specifically, under the present approach, program code is structured so that the segmentation and binarization functions/modules (and optionally a blob analysis function/module) are merged into a single module to reduce memory bandwidth. In addition, each image frame is segmented into a plurality of partitions (e.g., vertical strips) to enhance the reusability of the image data in LS already fetched from main memory. Each partition is then processed by a separate one of a plurality of processing engines, thereby increasing the utilization of all processing engines and allowing the processing engines to maintain good bandwidth. | 08-13-2009 |
| 20090213522 | ON-CHIP ADJUSTMENT OF MIMCAP AND VNCAP CAPACITORS - One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors. | 08-27-2009 |
| 20090240637 | RESILIENT CLASSIFIER FOR RULE-BASED SYSTEM - A resilient classifier for using with a rule-based system is provided. A system for classifying data for a rule-based system, may include: a system(s) for generating two training data sets, one data set is generated from input data while the second data set is generated from disturbed data; a system for merging the two training data sets; and a system for training a data classifier with the merged training data sets. As a result, the classification of data becomes more accurate, including when disturbed data is encountered. | 09-24-2009 |
| 20090245615 | VISUAL INSPECTION SYSTEM - This solution relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a cell computing system. The invention provides a high performance machine vision system over the prior art and provides a method for executing image processing applications on a Cell and BPE3 image processing system. Moreover, implementations of the invention provide a machine vision system and method for distributing and managing the execution of image processing applications at a fine-grained level via a PCIe connected system. The hybrid system is replaced with the BPE3 and the switch is also eliminated from the prior in order to meet over 1 GB processing requirement. | 10-01-2009 |
| 20100064156 | VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. | 03-11-2010 |
| 20100082938 | DELEGATED VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP) - This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries. | 04-01-2010 |
| 20100082941 | DELEGATED VIRTUALIZATION IN A MULTI-CORE PROCESSOR (MCP) - The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. | 04-01-2010 |
| 20100082942 | VIRTUALIZATION ACROSS PHYSICAL PARTITIONS OF A MULTI-CORE PROCESSOR (MCP) - Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated. | 04-01-2010 |
| 20100127730 | Internal charge transfer for circuits - The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture. | 05-27-2010 |
| 20100131712 | PSEUDO CACHE MEMORY IN A MULTI-CORE PROCESSOR (MCP) - Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss. As such, the other L2 level cache memory units serve the original L2 cache memory unit as pseudo caches | 05-27-2010 |
| 20100131713 | MOUNTED CACHE MEMORY IN A MULTI-CORE PROCESSOR (MCP) - Specifically, under the present invention an available on-chip memory is coupled to another logic core or memory (e.g., cache) unit using a set of cache managers. Specifically, each cache manager is coupled to the input and output of a cache memory unit. This allows the assigned memory to become an extension of the same level cache, next level cache memory, or memory buffer. This also allows the recovery of a memory block whose logic core is not operational, and is used to improve cache memory performance of the system. It should be understood in advance the teachings herein are typically applied to a Multi-Core Processor (MCP), although this need not be the case | 05-27-2010 |
| 20100131716 | CACHE MEMORY SHARING IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system. | 05-27-2010 |
| 20100131717 | CACHE MEMORY BYPASS IN A MULTI-CORE PROCESSOR (MCP) - This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system. | 05-27-2010 |
| 20100207585 | RESERVING POWER FOR ELECTRONIC DEVICES - The present invention provides way to reserve power for electronic devices such as mobile devices. Specifically, under the present invention, a user can establish and/or change a setting/threshold corresponding to an amount of (battery) power available to the electronic device to be held in reserve. The setting can be a percentage of total available power (e.g., n %). Once set, this amount of power is held in reserve and is unavailable for use by the electronic device. Before to the total power available to the device is reduced to the amount of power set by the user (e.g., 1-n %), an alert will be issued. If the user wishes to use the power held in reserve, the user can input a previously established reserve power access code amount that will make the reserve power available to the electronic device. | 08-19-2010 |
| 20100295156 | STRUCTURE FOR SYMMETRICAL CAPACITOR - Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance. | 11-25-2010 |
| 20100325392 | HYBRID MULTI FUNCTION COMPONENT SYSTEM - This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of groups of sub-processing components. Under this arrangement, different technology cores and functional components, such as memory, are organized in a way that different technologies can collaborate as a system. | 12-23-2010 |
| 20110113038 | SEARCH TERM SECURITY - As indicated above, the present invention transparently inserts search arguments/terms (referred to as noise) into a search string so that the search arguments themselves would not be clearly evident when a user is searching. The inserted noise terms are related to the underlying search terms. This would confuse a mining program and/or hacker looking for sensitive material (such as intellectual property). When the search results are returned, any “hits” resulting from noise will be removed transparently from the overall results. The insertion and removal under the present invention provides a more secure level of searching, yet is completely transparent to the end user. The inserted random search arguments are germane contextually to the search string. | 05-12-2011 |
| 20110119253 | SECURING SEARCH QUERIES - In general, the present invention protects actual search queries submitted to web search engines using a set (i.e., at least one) of supplemental queries (hereinafter referred to as securing search queries). As a result, collections of search queries will not form statistically stable categories, and will not disclose the search subject. Any hits resulting from securing search queries will be filtered from results that are returned to the requestor. In addition, the securing search queries can be associated with protective Internet Protocol addresses to reduce the possibility of the requestor of the actual search query to be identified. | 05-19-2011 |
