Monzel
Carl Monzel, Eagan, MN US
Patent application number | Description | Published |
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20130163357 | Quantifying the Read and Write Margins of Memory Bit Cells - Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells. | 06-27-2013 |
Christoph Monzel, Bad Neustadt DE
Patent application number | Description | Published |
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20100026111 | STATOR FOR AN ELECTRICAL MACHINE WITH LIQUID COOLING - The invention relates to a stator ( | 02-04-2010 |
James A. Monzel, North Ferrisburg, VT US
Patent application number | Description | Published |
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20080256405 | COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS - A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip. | 10-16-2008 |