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Montrym

Eric Thomas Montrym, Schenectady, NY US

Patent application numberDescriptionPublished
20110123327BEARING ASSEMBLY USING DIFFERENT TYPE THRUST BEARINGS - A bearing assembly includes a thrust bearing casing surrounding a rotating shaft at a location intermediate ends of the rotating shaft, the rotating shaft including an active side shaft thrust plate and an inactive side shaft thrust plate, each of the active side and the inactive side shaft thrust plate affixed to and extending radially from the rotating shaft, wherein the active side shaft thrust plate receives a substantially larger axial force compared to the inactive side shaft thrust plate during operation of the rotating shaft; a first thrust bearing between the thrust bearing casing and the active side shaft thrust plate; and a second thrust bearing between the thrust bearing casing and the inactive side shaft thrust plate. The first thrust bearing and the second thrust bearing are of a different type, e.g., a tilting pad bearing and a land bearing including a tapered land and/or flat land.05-26-2011

John Montrym, Los Altos Hills, CA US

Patent application numberDescriptionPublished
20080284786Display System Having Floating Point Rasterization and Floating Point Framebuffering - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.11-20-2008
20100079471Display System Having Floating Point Rasterization and Floating Point Framebuffering - A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.04-01-2010

John S. Montrym, Los Altos Hills, CA US

Patent application numberDescriptionPublished
20090244074Apparatus, System, and Method For Using Page Table Entries in a Graphics System to Provide Storage Format Information For Address Translation - A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.10-01-2009
20110078537ERROR DETECTION AND CORRECTION FOR EXTERNAL DRAM - One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.03-31-2011
20110078544Error Detection and Correction for External DRAM - One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.03-31-2011

Patent applications by John S. Montrym, Los Altos Hills, CA US

John S. Montrym, Los Altos, CA US

Patent application numberDescriptionPublished
20100106921SYSTEM AND METHOD FOR CONCURRENTLY MANAGING MEMORY ACCESS REQUESTS - A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.04-29-2010