| Patent application number | Description | Published |
|---|
| 20090164962 | Method of Reducing Crosstalk Induced Noise in Circuitry Designs - A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver. The ending point of the spatial vector is the break point of the interconnect wire segment farther from the driver. The method may define a Cartesian coordinate system with respect to the origin. The Cartesian coordinate system may be orthogonal with the interconnect wire segments of the physical circuit wiring design. The method may define one or more geometry windows in the physical circuit wiring design and compare the spatial vectors in each geometry window. | 06-25-2009 |
| 20090206680 | Apparatus for Suppressing Mid-Frequency Noise in an Integrated Circuit Having Multiple Voltage Islands - An apparatus for suppressing mid-frequency noise in an integrated circuit having multiple voltage islands is disclosed. Voltage rails powered at higher nominal voltages are selectively connected to voltage rails powered at lower nominal voltages via controlled gates. During operation, a voltage rail in which voltage has decreased below a pre-determined threshold is coupled to a voltage rail powered at a higher nominal voltage for a pre-selected time interval. | 08-20-2009 |
| 20100259289 | Detecting Open Ground Connections in Surface Mount Connectors - A device may include a current source for connecting to a printed circuit board. The device may also include a first FET switch pack and a second FET switch pack for connecting to the surface mount connector of the printed circuit board. Additionally, the device may include a FET controller connected to the first FET switch pack and the second FET switch pack. The FET controller may be utilized for connecting a first FET and a second FET to the first region of the surface mount connector. The FET controller may be configured for supplying the current to the first region of the surface mount connector to produce at least one continuous heat signature characteristic of an improperly connected ground pin. A thermal monitoring module may be used to identify the improper physical connection. | 10-14-2010 |
