Patent application number | Description | Published |
20080201671 | METHOD FOR GENERATING TIMING EXCEPTIONS - A method for generating timing exceptions for integrated circuit (IC) designs is disclosed. The method includes synthesizing an input RTL description into a gate-level netlist mapped to a technology library; detecting timing critical paths in the netlist; and determining for each detected timing critical path whether it induces timing exceptions. The timing exceptions generated by the disclosed method include, but are not limited to, multi-cycle paths, clock domain crossing false paths, asynchronous false paths, functional false paths, combinational false paths, sequential false paths, timing false paths, and the like. | 08-21-2008 |
20140101630 | COMPUTER SYSTEM FOR GENERATING AN INTEGRATED AND UNIFIED VIEW OF IP-CORES FOR HIERARCHICAL ANALYSIS OF A SYSTEM ON CHIP (SOC) DESIGN - In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view'of the IP-core is generated. | 04-10-2014 |
20140282321 | SYSTEM AND METHOD FOR A HYBRID CLOCK DOMAIN CROSSING VERIFICATION - A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage. Results are then reiterated through the system back to the static CDC verification. | 09-18-2014 |
20140282322 | SYSTEM AND METHOD FOR FILTRATION OF ERROR REPORTS RESPECTIVE OF STATIC AND QUASI-STATIC SIGNALS WITHIN AN INTEGRATED CIRCUIT DESIGN - A system and method identify potentially static and/or quasi-static signals within an integrated circuit (IC), or portion thereof. Static and quasi-static signals may be identified in a design description of the IC by any one or more of: (1) a fan-out size exceeding some threshold, (2) a toggle frequency in a simulation trace that is below some threshold, and (3) a signal name that appears in a list accessed from the memory. Identification of static and quasi-static signals is performed, typically, as part of a verification process in order to flag cases where the verification system would otherwise indicate an error (e.g., at a clock domain crossing). Identifying a signal of the IC as being static or quasi-static improves the quality of results of verification and makes it easier for a prospective user to concentrate on actual rather than spurious issues reported during verification. | 09-18-2014 |
20140282347 | SYSTEM AND METHOD FOR STRENGTHENING OF A CIRCUIT ELEMENT TO REDUCE AN INTEGRATED CIRCUIT'S POWER CONSUMPTION - A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller. | 09-18-2014 |
20150143307 | SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEMICONDUCTOR DESIGNS INCLUDING ALREADY GATED PIPELINE DESIGN - The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods. | 05-21-2015 |
20150234959 | METHOD AND APPARATUS USING FORMAL METHODS FOR CHECKING GENERATED-CLOCK TIMING DEFINITIONS - A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods. | 08-20-2015 |
Patent application number | Description | Published |
20110122849 | METHODS AND APPARATUS FOR PROVIDING SILENCE PERIODS IN DIRECTIONAL COMMUNICATIONS NETWORKS - A method of facilitating a silence period in a directional communication network is provided. The method may comprise initiating, by a first apparatus, a listening period mode, wherein the listening period mode comprises ceasing at least a portion of current communication and configuring the first apparatus to receive a request to initiate a new communication, determining whether a request is received during a time period in the listening period mode, and transmitting a response if the request to initiate the new communication is received during the time period in the listening period mode. | 05-26-2011 |
20130128808 | APPARATUS AND METHODS FOR MEDIA ACCESS CONTROL HEADER COMPRESSION - Systems, methods, and devices for communicating packets having a plurality of types are described herein. In some aspects, the packets include a compressed MAC header. In some aspects the packets include an acknowledgment (ACK) frame. The fields included in a particular packet type may be based on the type of information to be communicated to the receiving device. | 05-23-2013 |
20130128809 | APPARATUS AND METHODS FOR MEDIA ACCESS CONTROL HEADER COMPRESSION - Systems, methods, and devices for communicating packets having a plurality of types are described herein. In some aspects, the packets include a compressed MAC header. In some aspects the packets include an acknowledgment (ACK) frame. The fields included in a particular packet type may be based on the type of information to be communicated to the receiving device. | 05-23-2013 |
20130315139 | METHODS, DEVICES, AND SYSTEMS FOR EFFICIENT RETRANSMISSION COMMUNICATIONS - Methods, devices, and systems for retransmitting Media Access Control (MAC) protocol data units (MPDUs) in a multi-user multiple-input and multiple-output (MU-MIMO) communication system are disclosed. Concurrent data streams within a first transmission window are transmitted. Each concurrent data stream is associated with a different recipient and includes an equal number of MPDUs. An indication of a retransmission subset of the MPDUs to be retransmitted for each concurrent data stream may be obtained if errors are present. The retransmission subset for each concurrent data stream is retransmitted within a second transmission window. A length of the second transmission window is as long as the longest of the retransmission subsets of the concurrent data streams. One or more new MPDUs may be added to the concurrent data streams in the second transmission window so that each concurrent data stream in the second transmission window carries a same number of MPDUs. | 11-28-2013 |
20140108401 | System and Method for Adjusting Distributions of Data Using Mixed Integer Programming - Exemplary embodiments of the present disclosure are related to systems, methods, and computer-readable medium to facilitate modifying a distribution of data elements to more closely resemble a reference distribution. In exemplary embodiments a modification constraint can be assigned to limit a modification of data elements in a subject distribution and a reference distribution can be identified. Data elements in the subject distribution can be programmatically modified to generate a modified distribution based on a reference distribution, wherein a modification of the data elements can be constrained in response to the modification constraint. | 04-17-2014 |