Patent application number | Description | Published |
20090010832 | PROCESS FOR THE PREPARATION OF FINELY DIVIDED PRECIPITATED SILICA - The present invention provides a process for the preparation of finely divided precipitated silica. Finely divided precipitated silica is prepared by neutralization of alkali silicate solution, under continuous stirring, at 60° to 90° C. in presence of alkali metal salt as coagulating agent, in various neutralization steps during which neutralization is interrupted for specific time. Further acidic silica sol, is added until 60 to 80% of total alkali is neutralized. The reaction mixture is then aged at least for 3 minute under continuous agitation, followed by circulation through centrifugal pump at an appropriate rate. | 01-08-2009 |
20130315805 | Process For Simultaneous Production Of Potassium Sulphate, Ammonium Sulfate, Magnesium Hydroxide And/Or Magnesium Oxide From Kainite Mixed Salt And Ammonia - The present invention provides an integrated process for the recovery of sulphate of potash (SOP), ammonium sulphate and surface modified magnesium hydroxide and/or magnesium oxide utilizing kainite mixed salt and ammonia as the only consumable raw materials. The process involves treating kainite mixed salt with water to obtain solid schoenite and a schoenite end liquor. The latter is desulphated using CaCl | 11-28-2013 |
20150093309 | Method Of Recycling Of By-Products For The Production Of Soda Ash And Ammonium Sulphate - A method of producing soda ash and ammonium sulphate by recycling by-products of Merseberg and Solvay processes includes treating brine with soda ash distiller waste for desulphatation of the brine to obtain gypsum, recovering pure salt from the desulphated brine and utilizing it in manufacture of soda ash in a Solvay process, washing the gypsum and reacting it with liquor ammonia and carbon dioxide to obtain CaCO | 04-02-2015 |
Patent application number | Description | Published |
20130114715 | Delayed Duplicate I-Picture for Video Coding - A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture. | 05-09-2013 |
20130272429 | Color Component Checksum Computation in Video Coding - Checksum computation for video coding is provided that breaks the dependency between the color components of a picture in the prior art. More specifically, rather than computing a single checksum for a picture as in the prior art, a separate checksum is computed for each color component. Computing a separate checksum for each color component enables parallel computation of the component checksums. Methods are provided for computing three separate checksums after a picture is decoded. Methods are also provided for computing three separate checksums on a largest coding unit basis, thus allowing the checksums for a picture to be computed as the picture is being decoded. | 10-17-2013 |
20140232938 | SYSTEMS AND METHODS FOR VIDEO PROCESSING - Several systems and methods for processing of video frames based on one or more video formats are disclosed. In an embodiment, a video processing system comprises a memory and a video engine. The memory stores a plurality of video frames, a primary set of instructions and a plurality of secondary sets of processing instructions. Each secondary set of processing instructions is associated with a video format. The video engine is loaded with the primary set of instructions and is configured to fetch one or more video frames and a secondary set of processing instructions from the memory based on the loaded primary set of instructions. The fetched secondary set of processing instructions corresponds to a video format determined for processing of the one or more video frames. The video engine performs processing of the one or more video frames based on the secondary set of processing instructions. | 08-21-2014 |
20140341271 | METHOD AND APPARATUS OF HEVC DE-BLOCKING FILTER - A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block. | 11-20-2014 |
20140341287 | Sample Adaptive Offset (SAO) Filtering in Video Coding - A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by the SAO component, an indication that deblocked pixel blocks of an LCU are available, and applying SAO filtering, by the SAO component, to each pixel block of pixel blocks of an SAO processing area corresponding to the LCU responsive to the indication, wherein pixels of each pixel block of the SAO processing area are filtered in parallel. | 11-20-2014 |
20140355691 | MULTI-THREADING IN A VIDEO HARDWARE ENGINE - A video hardware engine with multi-threading functionality is disclosed. The video hardware engine includes a video hardware accelerator unit and a controller. The controller is coupled to the video hardware accelerator unit. The controller operates in an encode mode and a decode mode. In the encode mode, the controller receives a plurality of frames and encode attributes associated with each frame of the plurality of frames. The encode attributes associated with a frame of the plurality of frames is processed to generate encode parameters associated with the frame. The video hardware accelerator unit is configured to process the frame based on the encode parameters to generate an output. The output of the video hardware accelerator unit is processed to generate a compressed bit-stream and an encode status. In decode mode, the controller receives a compressed bit-stream and decode attributes and generates a plurality of frames and a decode status. | 12-04-2014 |
20140369419 | EFFICIENT BIT-PLANE DECODING ALGORITHM - A bitplane decoding system where the bitplane operations are broken up into an optimized plurality of sub-tasks. A pipeline structure is established for the execution of said sub-tasks on a plurality of processors or dedicated hardware logic blocks in a manner that allows efficient execution of the sub-tasks in parallel across two processors, resulting in a significant increase in performance. | 12-18-2014 |
20150036738 | METHOD AND APPARATUS FOR REAL-TIME SAO PARAMETER ESTIMATION - The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder. | 02-05-2015 |
20150207974 | METHODS AND APPARATUS TO GENERATE WIDE DYNAMIC RANGE IMAGES - Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs. | 07-23-2015 |
20150271494 | LOW POWER ULTRA-HD VIDEO HARDWARE ENGINE - A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N. | 09-24-2015 |
20150271512 | DYNAMIC FRAME PADDING IN A VIDEO HARDWARE ENGINE - A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame. | 09-24-2015 |
20150296212 | Processor Instructions for Accelerating Video Coding - A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding. | 10-15-2015 |
20150304648 | Ensuring Imaging Subsystem Integrity in Camera Based Safety Systems - A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly. | 10-22-2015 |
Patent application number | Description | Published |
20150019318 | GUI-BASED WALLET PROGRAM FOR ONLINE TRANSACTIONS - Provided is a method and a GUI-based software application that acts as a wallet with network interconnectivity for enabling a user to securely and seamlessly conduct transactions with his or her online financial transaction program by means of a computer or a wireless handheld device without having to depend on an Internet browser. | 01-15-2015 |
20150019319 | GUI-BASED WALLET PROGRAM FOR ONLINE TRANSACTIONS - Provided is a method and a GUI-based software application that acts as a wallet with network interconnectivity for enabling a user to securely and seamlessly conduct transactions with his or her online financial transaction program by means of a computer or a wireless handheld device without having to depend on an Internet browser. | 01-15-2015 |
20150019330 | GUI-BASED WALLET PROGRAM FOR ONLINE TRANSACTIONS - Provided is a method and a GUI-based software application that acts as a wallet with network interconnectivity for enabling a user to securely and seamlessly conduct transactions with his or her online financial transaction program by means of a computer or a wireless handheld device without having to depend on an Internet browser. | 01-15-2015 |
20150019333 | GUI-BASED WALLET PROGRAM FOR ONLINE TRANSACTIONS - Provided is a method and a GUI-based software application that acts as a wallet with network interconnectivity for enabling a user to securely and seamlessly conduct transactions with his or her online financial transaction program by means of a computer or a wireless handheld device without having to depend on an Internet browser. | 01-15-2015 |
20150019420 | GUI-BASED WALLET PROGRAM FOR ONLINE TRANSACTIONS - Provided is a method and a GUI-based software application that acts as a wallet with network interconnectivity for enabling a user to securely and seamlessly conduct transactions with his or her online financial transaction program by means of a computer or a wireless handheld device without having to depend on an Internet browser. | 01-15-2015 |
20150019421 | GUI-BASED WALLET PROGRAM FOR ONLINE TRANSACTIONS - Provided is a method and a GUI-based software application that acts as a wallet with network interconnectivity for enabling a user to securely and seamlessly conduct transactions with his or her online financial transaction program by means of a computer or a wireless handheld device without having to depend on an Internet browser. | 01-15-2015 |