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Mizutani, Kawasaki
Kazuhiro Mizutani, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090102010 | SEMICONDUCTOR DEVICE WITH STI AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area. | 04-23-2009 |
| 20110244650 | SEMICONDUCTOR DEVICE WITH STI AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area. | 10-06-2011 |
| 20110280072 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder. | 11-17-2011 |
Kouji Mizutani, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20080291757 | SIGNAL MASKING METHOD, SIGNAL MASKING CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A signal masking circuit includes a detection circuit, a delayed read data strobe signal generation circuit, a gating circuit, a counting circuit, and a masking circuit. The detection circuit detects a period of a logic “L” of a read data strobe signal. The gating circuit gates a delayed read data strobe signal, and generates a first masked read data strobe signal. The counting circuit counts the falls of the first masked read data strobe signal until the count reaches a predetermined number, and generates a masking signal for masking the first masked read data strobe signal. The masking circuit masks the first masked read data strobe signal, and outputs a second masked read data strobe signal. | 11-27-2008 |
Masami Mizutani, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100202661 | MOVING OBJECT DETECTION APPARATUS AND COMPUTER READABLE STORAGE MEDIUM STORING MOVING OBJECT DETECTION PROGRAM - The approaching object detection unit in a moving object detection apparatus for a moving picture calculates a moving distance of each characteristic point in an image frame obtained at time point t−1, on the basis of an image frame obtained at time point t and an image frame obtained at time point t−1, and on the basis of the image frame obtained at time point t−1 and an image frame obtained at time point t+m, a moving distance of a characteristic point is in the image frame obtained at time point t−1 and has a moving distance to be less than a prescribed value. | 08-12-2010 |
| 20110063436 | DISTANCE ESTIMATING APPARATUS - A distance estimating apparatus includes a mirror, a camera device for obtaining an original image including a real image of the object and a mirror image of the object mirrored by the mirror, and a processor for calculating a distance between the camera device and the object on the basis of a correlation of a position of the real image included in the original image and a position of the mirror image included in the image. | 03-17-2011 |
| 20110292210 | MEASUREMENT DEVICE, CONTROL DEVICE, AND STORAGE MEDIUM - A measurement device includes: a plurality of calculation units configured to calculate a noise intensity, for a monitor area in an image data obtained by a camera having a plurality of image sensors, based on a pixel value of each of a plurality of pixels of the monitor area, and each of the plurality of calculation units calculates the noise intensity for different monitor areas in the image data; a selection unit configured to select a noise intensity from noise intensities calculated by each of the plurality of calculation units; and an output unit configured to output information based on the noise intensity selected by the selection unit. | 12-01-2011 |
| 20120121127 | IMAGE PROCESSING APPARATUS AND NON-TRANSITORY STORAGE MEDIUM STORING IMAGE PROCESSING PROGRAM - An image processing apparatus executes acquiring, on a first image having a pattern having first areas and second areas that have a different color from the first areas, center position of the pattern where the first areas and the second areas cross, acquiring boundary positions between the first and second area, converting the first image to a second image having its image distortion corrected by using the center position and the boundary positions, acquiring, by scanning on the second image, expectation values which are areas including the point where the first and second areas cross excluding the center position, acquiring a intersection position of the intersection on the second image based on the expectation values, acquiring the center position and the positions on the first image corresponding to the intersection position by inverting the second image to the first image, determining the points corresponding to the acquired positions as features. | 05-17-2012 |
| 20120121137 | IMAGE PROCESSING APPARATUS - An image processing program causes a computer to execute processing of obtaining an image, photographed with a camera, of markers disposed in a real space, creating vectors from the camera and to the markers, selecting a reference marker from the markers, calculating a inner product of the vectors, canceling use of a negative sign included in an equation that obtains a distance between the camera and a remaining marker, creating sign patterns based on to the cancelled remaining markers, setting a first distance between the reference marker and the camera, calculating candidates of a distance between the camera and the remaining markers, calculating error between an inter-marker distance in a real space and the sign patterns, calculating other error when a second distance is set, determining the distance according to the error and the other error, and calculating a position and pose of the camera according to the determined distance. | 05-17-2012 |
Masayoshi Mizutani, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100098100 | Media gateway device - A media gateway device includes a first specific call control unit performing line connection control of one of plural interconnection units and plural second call control units requesting the first specific call control unit to perform the line connection control of one of the plural interconnection units. The first specific call control unit has a management data storage unit storing management data for determining which one of the plural interconnection units controls which line of the public network. Each of the plural second call control units has a control request unit requesting the first specific call control unit to perform line connection control of one of the plural interconnection units. | 04-22-2010 |
Michiyuki Mizutani, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20120137006 | COMPUTING SYSTEM AND COMPUTING SYSTEM MANAGEMENT METHOD - A computing system includes: a plurality of computing machines and a load balancer configured to allocate computing processing to the plurality of computing machines. In the computing system, the plurality of computing machines executes the computing processing, each of the plurality of computing machines includes an execution instruction unit that instructs to execute one of garbage collection (GC) and restart of the computing machine. The computing machine, in an active state in which the computing processing is allowed to be executed, switches a state of another standby computing machine to an active state when the active computing machine is instructed to execute one of the GC and the restart of the computing machine, and starts one of the GC and the restart of the computing machine after the switching is completed. | 05-31-2012 |
Ryo Mizutani, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100175037 | METHOD, APPARATUS, AND PROGRAM FOR CORRECTING HOLD ERROR - A hold error correction method for complicated large scale integration in a semiconductor is provided. Based on timing analyses, hold error path start point information including a set of a hold error amount at a start point and a minimum value in set-up margins for all data paths starting from the start point, and hold error path end point information including a set of a hold error amount at an end point and a minimum value in set-up margins for all data paths reaching the end point, in association with a failed hold error path, is obtained. The hold error path is classified based on whether the hold error is correctable according to the obtained information. The correctable hold error path is grouped based on a certain criterion. Finally, which of the start point and the end point a delay buffer is inserted into is determined per group. | 07-08-2010 |
Yasushi Mizutani, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20080273603 | DIFFERENTIAL SIGNAL TRANSMITTING APPARATUS AND DIFFERENTIAL SIGNAL RECEIVING APPARATUS - A differential signal transmitting apparatus for transmitting a differential signal through two transmission lines. The apparatus includes: transmitting-side board connecting terminals | 11-06-2008 |
| 20090244798 | POWER STATUS NOTIFICATION METHOD AND POWER STATUS NOTIFICATION CIRCUIT - A power status notification method notifying a first device that a second power supply of a second device different from a first power supply of the first device is turned off, where a source voltage of the first power supply is different from a source voltage of the second power supply. The power status notification method and circuit include supplying the first device with a low-level notification signal indicating a power off state of the second power supply in a case where the source voltage of the second power supply drops to a predetermined voltage or is less than the predetermined voltage and setting the predetermined voltage at a value higher than a threshold level at which a circuit of the first device supplied with the notification signal recognizes as a low level. | 10-01-2009 |