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| 20090290553 | BASE STATION APPARATUS, COMMUNICATION SYSTEM AND COMPUTER PROGRAM - There is provided a base station apparatus which allocates communication bands for terminal units from an available communication band, and performs wireless communications with the terminal units using the allocated communication bands, including: a priority table storing priority information used for deriving a priority of the communication; a detecting part detecting a situation change concerning the communications; a band derivation part deriving communication bands required for the communications with terminal units to communicate, when the detecting part detects the situation change; a priority derivation part deriving priorities of the communications with the terminal units on the basis of the priority information stored in the priority table; and an allocating part allocating the communication bands derived by the band derivation part for the wireless communications with the terminal units in the order of descending priorities derived by the priority derivation part. | 11-26-2009 |
| 20100030849 | Server apparatus for thin-client system - A server apparatus for a thin-client system includes: a receiver unit that receives an input event from the terminal device; an input event processing unit that applies the received input event to particular processing related to the received input event; a region determiner unit that dynamically determines, as a desired region, a partial image region from a resultant display picture generated by the particular processing, so that the partial image region is affected by the particular processing; a region image generator unit that generates, as partial image information, partial image data and position data of the desired region, according to data of the display picture; and a transmitter unit that transmits the generated partial image information to the terminal device. | 02-04-2010 |
| 20100192152 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM - An information processing device which has a plurality of process units for performing various kinds of processes includes a detecting unit that detects a processing loads of the process units; a determining unit that determines whether a total amount of the processing loads detected by the detecting unit is equal to or larger than a specific value; a designating unit that designates a process unit having a process state to be controlled, based on the processing loads of the process units detected by the detecting unit, when the determining unit determines that the total amount is equal to or larger than the specific value; a process identifying unit that identifies a process having an execution state to be controlled among processes being performed by the process unit designated by the designating unit; and a control unit that controls the execution state of the process identified by the process identifying unit. | 07-29-2010 |
| 20100251255 | SERVER DEVICE, COMPUTER SYSTEM, RECORDING MEDIUM AND VIRTUAL COMPUTER MOVING METHOD - A server device which operates a plurality of virtual computers so as to respectively correspond to a plurality of terminal devices to which physical devices are connected, the server device includes a judging unit that judges whether move of each of the plurality of virtual computers to each of the plurality of terminal devices is possible; a moving unit that moves one corresponding virtual computer to one terminal device move of the corresponding virtual computer to which has been judged to be possible using the judging unit; and an allocating unit that allocates one physical device connected to the terminal device concerned to the virtual computer which has been moved to the terminal device using the moving unit. | 09-30-2010 |
| 20110154333 | MACHINE SYSTEM, INFORMATION PROCESSING APPARATUS, METHOD OF OPERATING VIRTUAL MACHINE, AND PROGRAM - An information processing apparatus includes: a first virtual machine part to operate by being allocated to another information processing apparatus; a monitoring-application information storing part to store an application for monitoring the operation of the virtual machine part; a determining part to determine, in the virtual machine part, whether the application stored in the monitoring-application information storing part is operating by accessing an auxiliary storage device connected to the other information processing apparatus; a status storing part to store application information related to an operating status of the application when the determining part determines that the application is operating; an application exiting part to exit the application when the application information is stored; and a transmitting part to transmit virtual-machine information related to an operating status of the virtual machine part, together with the stored application information, to the other information processing apparatus when the application is exited. | 06-23-2011 |
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| 20090198385 | STORAGE MEDIUM FOR STORING POWER CONSUMPTION MONITOR PROGRAM, POWER CONSUMPTION MONITOR APPARATUS AND POWER CONSUMPTION MONITOR METHOD - A power consumption monitor device monitors power consumption of one or more devices through a network. The monitor device includes a storage unit, a load information collecting unit and a power consumption estimation unit. The storage unit stores power consumption estimation information indicating a relation between power consumption and processing load of the one or more devices. The load information collecting unit collects load information indicating the processing load of the one or more devices through the network to the monitor device. The power consumption estimation unit estimates power consumption of the one or more device based on the collected load information and the power consumption estimation information. | 08-06-2009 |
| 20090254702 | RECORDING MEDIUM STORING DATA ALLOCATION CONTROL PROGRAM, DATA ALLOCATION CONTROL DEVICE, DATA ALLOCATION CONTROL METHOD, AND MULTI-NODE STORAGE-SYSTEM - A data allocation control program manages data allocation when data is distributively stored in a plurality of disk nodes that are shifted to a power saving mode unless access is performed for a certain time. The program produces a plurality of allocation pattern candidates each indicating the disk nodes in which the respective data are to be stored. The program calculates a no-access period expectation that represents an expected value of occurrence of a no-access period during which access is not performed to some of the disk nodes. The program selects as an allocation pattern for data reallocation, one of the plurality of produced allocation pattern candidates with the largest calculated no-access period expectation. The program instructs the disk nodes to reallocate the respective data in accordance with the selected allocation pattern. | 10-08-2009 |
| 20090282287 | SUPPORTING APPARATUS FOR ANALYZING COMPUTER OPERATION STATUS - Processing time required from transmission of a request packet including a processing request from a client, until return of a reply packet in which internal information including an operation status of a plurality of servers is added to an execution result of processing corresponding to the processing request, obtained by the servers in cooperation with each other, is calculated by a function incorporated beforehand in the respective servers. Moreover, the internal information added to the reply packet is extracted and stored in an internal information DB in association with the calculated required time of the processing. Furthermore predetermined statistical processing is performed with respect to the internal information and the required time associated with the internal information stored in the internal information DB to analyze the operation status of the plurality of servers. | 11-12-2009 |
| 20090319724 | DISTRIBUTED DISK CACHE SYSTEM AND DISTRIBUTED DISK CACHE METHOD - According to an aspect of the embodiment, a packet analyzing apparatus monitors a concentration level of input and output access from an access apparatus to a disk device, specifies a data area to which the concentration level of input and output access exceeds a first threshold, and instructs a storage server to cache the data area. The packet analyzing apparatus monitors a concentration level of input and output access to a data area to which the data area is cached, and, when the concentration level of input and output access is below a second threshold, instructs the storage server to release the caching. | 12-24-2009 |
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| 20080244159 | DATA TRANSFER CONTROL APPARATUS AND DATA TRANSFER CONTROL METHOD - A data transfer control apparatus includes a memory, a write control part controlling data writing to the memory, a read control part controlling data reading from the memory, a read-start calculation part calculating an output timing of a notification which indicates a read-start operation to the read control part based on each transfer condition of the data writing to the memory and the data reading from the memory, and an asynchronous transfer part asynchronously transferring a clock of the notification, and notifying the read control part of the notification. | 10-02-2008 |
| 20090027988 | Memory device, memory controller and memory system - An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals. | 01-29-2009 |
| 20100146201 | MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM - Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks. | 06-10-2010 |
| 20100172200 | MEMORY DEVICE, MEMORY CONTROLLER AND MEMORY SYSTEM - Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks. | 07-08-2010 |
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| 20090019325 | MEMORY DEVICE, SUPPORTING METHOD FOR ERROR CORRECTION THEREOF, SUPPORTING PROGRAM THEREOF, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A memory device (memory module) having one or a plurality of memory chips is disclosed. By including in a memory chip an error generation part to generate an error, an error is generated in a specific area of a memory in accordance with an address specification, thereby confirmation of an ECC function is facilitated. The error generation part includes an error code generation part that generates an error code. The memory chip is configured by one or a plurality of memory matrixes. | 01-15-2009 |
| 20090021991 | MEMORY DEVICE, CONTROL METHOD FOR THE SAME, CONTROL PROGRAM FOR THE SAME, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC EQUIPMENT - A memory device having a single or a plurality of memory chips includes a memory part (control register, SPD memory unit) inside each memory chip, which memory part stores control data concerning the memory chip. The memory device enables writing-in or readout of the control data stored on the memory part to be able to set any desired control data for each memory chip, and, when the memory device has the plurality of memory chips, enables separate use of each of the memory chips. | 01-22-2009 |
| 20090034342 | MEMORY DEVICE, CONTROL METHOD FOR THE SAME, CONTROL PROGRAM FOR THE SAME, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC EQUIPMENT - A memory device includes a single or a plurality of memory chips. In the memory device (memory module), the single memory chip or each of the plurality of memory chips has a memory part storing control data such as specification data and function data, and control data stored on the memory part is rewritable. Control data stored on the memory part separately disposed on each memory chip enables separate use of the memory chip, which improves compatibility and flexibility of the memory. | 02-05-2009 |
