| Patent application number | Description | Published |
|---|
| 20080320433 | Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit- board manufacturing method - An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file. | 12-25-2008 |
| 20090049419 | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method - An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. When performing a DRC, as for in an FPGA, a DRC unit checks an attribute of a pin and the like by referring to the FPGA information that is retrieved from the FPGA-designing CAD apparatus and stored in a FPGA-information storing unit by the FPGA-information managing unit. | 02-19-2009 |
| 20090184408 | Semiconductor device for fingerprint recognition - A semiconductor device is disclosed that performs fingerprint recognition on the electrostatic-capacity principle. A finger sweeping across a fingerprint recognition area of a semiconductor chip provides positive fingerprint recognition operations with improved reliability. | 07-23-2009 |
| 20090248915 | COMMUNICATION CONTROL APPARATUS AND COMMUNICATION CONTROL METHOD - A communication control apparatus includes a communication terminal capable of performing communication with an external apparatus. The communication control apparatus includes virtual interfaces for separately receiving, through a communication terminal, plural sets of access information representing respective specifics of I/O accesses which are output to one I/O device from a plurality of virtual processing units in the external apparatus. The communication control apparatus includes a match determination unit for comparing the plural sets of access information received from the external apparatus by the virtual interfaces, and determining whether the plural sets of access information are matched with each other. The communication control apparatus includes an access control unit for, when the plural sets of access information received by the plurality of virtual interfaces are matched with each other, sending the relevant access information to the I/O device that is an access destination of the relevant access information. | 10-01-2009 |
| 20090249034 | PROCESSOR AND SIGNATURE GENERATION METHOD, AND MULTIPLE SYSTEM AND MULTIPLE EXECUTION VERIFICATION METHOD - A processor performs instruction execution regardless of a program order. An execution unit executes an instruction, and transmits end information of the instruction whose execution has ended. A retire unit receives the end information, rearranges a result of the instruction whose execution has ended in a program order to determine the instruction execution, and transmits completed instruction information which reports that the instruction execution has been determined. A signature generation unit receives the completed instruction information from the retire unit, and generates a signature using the completed instruction information. | 10-01-2009 |
| 20090249268 | WARNING DEVICE AND WARNING METHOD - A warning device checks for errors in design object data and issues a warning for detected errors by storing allowance information, which allows issuance of warning prevention, cancel information, which cancels relevant allowance information to permit issuance of warning for each error identification, and instruction identification, which identifies an edit command for editing generated design object data for error identification. When said edit command is accepted, the error identification for the instruction identification of edit command is acquired. Cancel information can be registered for error identification. Respective errors corresponding to error identifications are checked, when an operation for checking the design object data is accepted, and when a type of an error is identified, whether to issue a warning based on the allowance information and cancel information for relevant error identification is determined. | 10-01-2009 |
| 20100082875 | TRANSFER DEVICE - A transfer device includes: a first input port operatively connected to a first apparatus; a second input port operatively connected to a second apparatus which is to run in parallel to the first apparatus; an output port operatively connected to a third apparatus; and a controller for controlling a data synchronization in accordance with a process including: receiving first and second data packets from the first and second apparatus, respectively, each of the first and second data packets including a check code; comparing one of the check codes in the first and second data packet with the other; and transferring at least the data of one of the first and second data packets upon determining coincidence of the check codes of the first and second data packets to the third apparatus via the output port. | 04-01-2010 |
| 20100191512 | POWER SUPPLY DESIGN - In one embodiment, there is provided a method for a computer aiding a design of a power supply that includes extracting data of one of a plurality of power supplies of an apparatus from a product data about the apparatus, extracting data of a power supply system from a power supply system data, the power supply system is not allocated to any of the plurality of power supplies of the apparatus and associating the extracted data of the power supply with the extracted data of the power supply system in a power supply allocation result data. | 07-29-2010 |
