| Patent application number | Description | Published |
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| 20100038617 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction. | 02-18-2010 |
| 20100295013 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device according to an embodiment includes: a semiconductor substrate; a resistance element of a first conductivity type formed in one region of the semiconductor substrate; a field effect transistor of a second conductivity type formed in another region of the semiconductor substrate; and a field effect transistor of the first conductivity type formed in still another region of the semiconductor substrate. The resistance element includes: an insulating film formed in an upper layer portion of the semiconductor substrate; and a well of the first conductivity type formed immediately below the insulating film, an impurity concentration at an arbitrary depth position in the well of the first conductivity is lower than an impurity concentration at the same depth position in a channel region of the field effect transistor of the second conductivity type. | 11-25-2010 |
| 20110062509 | SEMICONDUCTOR DEVICE HAVING UPPER LAYER PORTION OF SEMICONDUCTOR SUBSTRATE DIVIDED INTO A PLURALITY OF ACTIVE AREAS - A semiconductor memory device includes: a semiconductor substrate; a plurality of element isolation insulators disposed in parts of an upper layer portion of the semiconductor substrate and dividing the upper layer portion into a plurality of active areas extended in one direction; tunnel insulating films provided on the active areas: charge storage members provided on the tunnel insulating films; and control gate electrodes provided on the charge storage members. A width of a middle portion of one of the active areas in the up-to-down direction being smaller than a width of a portion of the active areas upper of the middle portion and a width of a portion of the active areas below the middle portion. | 03-17-2011 |
| 20110062527 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SAME - In one embodiment, a semiconductor apparatus is disclosed. The apparatus includes: an element-isolation insulating film formed on a major surface of a semiconductor layer, the element-isolation insulating film having a first opening and a second opening; an n-type MOSFET provided in the first opening; and a p-type MOSFET provided in the first opening. An upper face of a portion of the element-isolation insulating film adjacent to a source/drain region of the n-type MOSFET is positioned below an upper face of the source/drain region of the n-type MOSFET. An upper face of a portion of the element-isolation insulating film adjacent to a source/drain region of the p-type MOSFET is positioned above an upper face of the source/drain region of the p-type MOSFET. | 03-17-2011 |
| 20110096600 | SEMICONDUCTOR MEMORY DEVICE REDUCING RESISTANCE FLUCTUATION OF DATA TRANSFER LINE - According to one embodiment, a semiconductor memory device includes first and second memory cell blocks and an interconnect rerouting unit provided therebetween. The first memory cell block includes first interconnects and second interconnects provided in each space between the first interconnects. The second memory cell block includes a plurality of third interconnects provided on lines extending from the first interconnects and a plurality of fourth interconnects provided on lines extending from the second interconnects. A width and a thickness of the second and fourth interconnects are smaller than a width and a thickness of the first and second interconnects. Each of the first to fourth interconnects is connected to one end of first to fourth cell units including memory cells. The interconnect rerouting unit connects one of the fourth interconnects to one of the first interconnects and connects one of the third interconnects to the second interconnects. | 04-28-2011 |
| Patent application number | Description | Published |
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| 20080268639 | Method of Manufacturing A Semiconductor Integrated Circuit Device - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 10-30-2008 |
| 20090140342 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME, A METHOD OF MANUFACTURING A VERTICAL MISFET AND A VERTICAL MISFET, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film. | 06-04-2009 |
| 20090275193 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 11-05-2009 |
| 20100136778 | Semiconductor Memory Device and a Method of Manufacturing the Same, A Method of Manufacturing a Vertical MISFET and a Vertical MISFET, and a Method of Manufacturing a Semiconductor Device and a Semiconductor Device - Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film. | 06-03-2010 |
| 20110021022 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 01-27-2011 |
