Patent application number | Description | Published |
20080203584 | Stacked-type semiconductor package - Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path. | 08-28-2008 |
20080224311 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises. | 09-18-2008 |
20090032973 | Semiconductor stack package having wiring extension part which has hole for wiring - A semiconductor stack package includes a first printed wiring board; a plurality of semiconductor chips stacked on the first printed wiring board, wherein among the semiconductor chips, the uppermost semiconductor chip has an electrode pad for providing power supply, a ground pad for providing grounding, and a signal pad for signal transmission in a center area on the upper surface of the chip; connection lands formed on the first printed wiring board on the outside of the stacked semiconductor chips; a wiring extension part which is formed on the uppermost semiconductor chip, and has wiring circuits extending from the center to the periphery thereof, wherein at least one of the electrode pad and the ground pad is electrically connected to one end of one of the wiring circuits; and a wire for connecting the other end of the relevant wiring circuit of the wiring extension part and one of the connection lands on the first printed wiring board. | 02-05-2009 |
20090140409 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length L | 06-04-2009 |
20090140412 | SEMICONDUCTOR DEVICE HAVING IMPROVED SOLDER JOINT AND INTERNAL LEAD LIFETIMES - A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer. | 06-04-2009 |
20090250801 | Semiconductor device - A semiconductor device in which a plurality of semiconductor elements are stacked, yet realizing high speed operation of the semiconductor elements. The semiconductor device is provided with semiconductor packages, and a spacer. The semiconductor packages are stacked, with the spacer interposed therebetween. The semiconductor packages have, respectively, package boards, and semiconductor elements mounted on the package boards. The spacer has a plurality of conductive vias and a capacitor element. The semiconductor packages are electrically connected through the conductive vias. The capacitor element is electrically connected, among the conductive vias, to a conductive via that electrically connects the semiconductor element and power supply, and a conductive via that electrically connects the semiconductor element and ground. | 10-08-2009 |
20090327981 | Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged - Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system. | 12-31-2009 |
20100095257 | ELECTROMAGNETIC FIELD ANALYSIS OF SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR CHIP MOUNTED THEREON - An electromagnetic field analysis of a semiconductor package with a semiconductor chip mounted thereon can be performed simply with a high accuracy. First modeling and second modeling of the semiconductor package with the semiconductor chip mounted thereon are carried out, thereby performing first and second electromagnetic field analyses. Results of the first and second electromagnetic field analyses are synthesized to determine electrical characteristics of the semiconductor package. Specifically, an inductance analysis is performed with the entire semiconductor chip regarded as a dielectric, thereby determining an inductance component of an equivalent circuit. A capacitance analysis is performed with the semiconductor chip regarded as a dielectric having a metal thin film on its surface, thereby determining a capacitance component of an equivalent circuit. Results of the inductance analysis and the capacitance analysis are synthesized to determine an equivalent circuit. | 04-15-2010 |
20100193929 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package board, first connectors, and a first multi-layered structure. The package board has first and second regions. The first connectors are in the first region. The first multi-layered structure includes a first semiconductor chip, a wiring board, and second to fifth connectors. The first semiconductor chip has first and second surfaces. The first surface covers the second region. The wiring board has third and fourth surfaces. The third surface is fixed to the second surface. The second to fourth connectors are in the center regions of the second to fourth surfaces, respectively. The fifth connectors are aligned along opposing two sides of the fourth surface. The second connectors electrically connect to the third connectors. The third connectors electrically connect to the fourth and fifth connectors. The first connectors electrically connect to the fourth and fifth connectors. | 08-05-2010 |
20100193933 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. | 08-05-2010 |
20100208443 | SEMICONDUCTOR DEVICE - A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates | 08-19-2010 |
20100213611 | SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes a first wiring layer including a signal wiring line formed therein, and a second wiring layer stacked on the first wiring layer and including a power-supply plane and/or ground plane formed therein, the power-supply plane or the ground plane is not formed at least within a part of the region of the second wiring layer facing the signal wiring line of the first wiring layer. | 08-26-2010 |
20100224984 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE IN WHICH CIRCUIT BOARD AND SEMICONDUCTOR CHIP ARE CONNECTED BY LEADS - A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted. | 09-09-2010 |
20100289141 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that has a large number of external connection terminals. The package substrate includes a slot, the external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The bonding finger arrangement includes a first bonding finger array, which is located at a close distance from the each longer side of the slot, and a second bonding finger array, which is located at a distance farther than the distance of the first bonding finger array from the each longer side of the slot. The central section of the bonding finger area includes at least the second bonding finger array, and the end sections of the bonding finger area includes the first bonding finger array. | 11-18-2010 |
20100295162 | Semiconductor device - Portions of a wiring layer extending like cantilevers from an inner peripheral edge of an opening in a substrate are joined to respective terminals of a semiconductor chip mounted on the substrate. A junction portion between each portion of the wiring layer and the corresponding terminal is sealed with resin. | 11-25-2010 |
20100295179 | BGA SEMICONDUCTOR DEVICE HAVING A DUMMY BUMP - A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps. | 11-25-2010 |
20100314779 | SEMICONDUCTOR DEVICE THAT SUPPRESSES MALFUNCTIONS DUE TO NOISE GENERATED IN INTERNAL CIRCUIT - A semiconductor device includes a first pad row and a second pad row, a first ground potential supply electrode which is connected to a first interconnect provided near the first pad row, and a second ground potential supply electrode which is connected to a second interconnect provided near the second pad row. The first pad row includes a first pad connected to the first circuit within the chip and connected to the first interconnect via a first bonding wire, and includes a second pad connected to a second circuit within the chip and connected to the second interconnect via a second bonding wire crossing over the second pad row. | 12-16-2010 |
20110063936 | SEMICONDUCTOR DEVICE INCLUDING PLURAL ELECTRODE PADS - A semiconductor device includes a pad for sense amplifier ground potential as an electrode pad supplying ground potential voltage to a sense amplifier, a first conductive line connected to the pad for sense amplifier ground potential, and a second conductive line connected to an electrode pad closest to the pad for sense amplifier ground potential among plural electrode pads included in a pad row. The second conductive line extends to the opposite side of the first conductive line with the pad row as a reference. | 03-17-2011 |
20110084395 | Semiconductor package substrate and semiconductor device having the same - A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality. | 04-14-2011 |
20110180934 | SEMICONDUCTOR DEVICE - A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively. | 07-28-2011 |
20120061826 | SEMICONDUCTOR DEVICE - A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad. | 03-15-2012 |
20120119387 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 05-17-2012 |
20120146242 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a wiring board, a stack of semiconductor chips, and a first sealing member. The wiring board has a first surface. The wiring board includes a first insulating layer formed over the first surface. The first insulating layer has a first opening. The stack of semiconductor chips is mounted over the first surface of the wiring board. The stack of semiconductor chips includes a first semiconductor chip. The first semiconductor chip is closer to the wiring board than the other semiconductor chips. The first sealing member seals at least the first semiconductor chip. The first sealing member includes a protruding portion. The first opening of the insulating layer faces toward the protruding portion of the first sealing member. | 06-14-2012 |
20120200159 | SEMICONDUCTOR DEVICE - A semiconductor device includes: first and second power supply wirings VDDQ and VSSQ, respectively; an output circuit | 08-09-2012 |
20120302007 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS WITH DIFFERENT THICKNESS - In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip. | 11-29-2012 |
20130093083 | SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted. | 04-18-2013 |
20130114223 | SEMICONDUCTOR DEVICE - A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates | 05-09-2013 |
20130127048 | DEVICE - A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter. | 05-23-2013 |
20130140674 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. | 06-06-2013 |
20130277835 | SEMICONDUCTOR DEVICE - A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad. | 10-24-2013 |
20140035166 | SEMICONDUCTOR DEVICE STACK WITH BONDING LAYER AND WIRE RETAINING MEMBER - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip. | 02-06-2014 |
20140094000 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array. | 04-03-2014 |
20140103542 | SEMICONDUCTOR PACKAGE WITH BONDING WIRES OF REDUCED LOOP INDUCTANCE - A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers. | 04-17-2014 |
20150022255 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. | 01-22-2015 |