Patent application number | Description | Published |
20090271980 | METHOD FOR CONTROLLING WARPAGE IN REDISTRIBUTED CHIP PACKAGING PANELS - A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly. | 11-05-2009 |
20100006988 | Integrated Conformal Shielding Method and Process Using Redistributed Chip Packaging - An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules ( | 01-14-2010 |
20100127394 | THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming ( | 05-27-2010 |
20100276767 | MEMS MICROPHONE WITH CAVITY AND METHOD THEREFOR - A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. The cavity is formed in the substrate directly opposite the MEMS structure. The cavity has an opening formed on the second side. The dielectric film is attached to the second side of the substrate and completely covering the opening. In one embodiment, the MEMS structure is a diaphragm for a microphone. Another embodiment includes a method for forming the device. | 11-04-2010 |
20110156266 | METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit. | 06-30-2011 |
20120021565 | METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE - A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface. | 01-26-2012 |
20130049217 | SEMICONDUCTOR DEVICE PACKAGING HAVING PRE-ENCAPSULATION THROUGH VIA FORMATION USING DROP-IN SIGNAL CONDUITS - A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications. | 02-28-2013 |
20130154091 | SEMICONDUCTOR DEVICE PACKAGING USING ENCAPSULATED CONDUCTIVE BALLS FOR PACKAGE-ON-PACKAGE BACK SIDE COUPLING - A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package. | 06-20-2013 |
20130207255 | SEMICONDUCTOR DEVICE PACKAGE HAVING BACKSIDE CONTACT AND METHOD FOR MANUFACTURING - A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive. | 08-15-2013 |
20140167247 | SEMICONDUCTOR DEVICE PACKAGE HAVING BACKSIDE CONTACT AND METHOD FOR MANUFACTURING - A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive. | 06-19-2014 |
20150014838 | MICROELECTRONIC PACKAGES HAVING FRONTSIDE THERMAL CONTACTS AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes forming one or more redistribution layers over an encapsulated die having a frontside bond pad area and a frontside passivated non-bond pad area. The redistribution layers are formed to have a frontside opening over the non-bond pad area of the encapsulated die. A primary heat sink body is provided in the frontside opening and thermally coupled to the encapsulated die. A contact array is formed over the redistribution layers and is electrically coupled to a plurality bond pads located on the frontside bond pad area of the encapsulated die. | 01-15-2015 |
20150014855 | MICROELECTRONIC PACKAGES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers. | 01-15-2015 |
20150115454 | MICROELECTRONIC PACKAGES HAVING LAYERED INTERCONNECT STRUCTURES AND METHODS FOR THE MANUFACTURE THEREOF - Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure. | 04-30-2015 |
20150270233 | WAFER LEVEL PACKAGES AND METHODS FOR PRODUCING WAFER LEVEL PACKAGES HAVING DELAMINATION-RESISTANT REDISTRIBUTION LAYERS - Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer. | 09-24-2015 |
Patent application number | Description | Published |
20100319815 | METHOD OF MAKING SHAPE MEMORY ALLOY ARTICLES WITH IMPROVED FATIGUE PERFORMANCE - A method of making articles made of shape memory alloys having improved fatigue performance and to methods of treating articles formed from shape memory alloy materials by pre-straining the articles (or desired portions of the articles) in a controlled manner so that the resultant articles exhibit improved fatigue performance. The shape memory articles are preferably medical devices, more preferably implantable medical devices. They are most preferably devices of nitinol shape memory alloy, most particularly that is superelastic at normal body temperature. The pre-straining method of the present invention as performed on such articles includes the controlled introduction of non-recoverable tensile strains greater than about 0.20% at the surface of a desired portion of a shape memory alloy article. Controlled pre-straining operations are performed on the shape-set nitinol metal to achieve non-recoverable tensile strain greater than about 0.20% at or near the surface of selected regions in the nitinol metal article. The pre-straining operations result in a significant increase in fatigue life of the selectively treated regions and an overall improvement in the fatigue performance of the device. | 12-23-2010 |
20100331946 | SHAPE MEMORY ALLOY ARTICLES WITH IMPROVED FATIGUE PERFORMANCE AND METHODS THEREFORE - Articles made of shape memory alloys having improved fatigue performance and to methods of treating articles formed from shape memory alloy materials by pre-straining the articles (or desired portions of the articles) in a controlled manner so that the resultant articles exhibit improved fatigue performance. The shape memory articles are preferably medical devices, more preferably implantable medical devices. They are most preferably devices of nitinol shape memory alloy, most particularly that is superelastic at normal body temperature. The pre-straining method of the present invention as performed on such articles includes the controlled introduction of non-recoverable tensile strains greater than about 0.20% at the surface of a desired portion of a shape memory alloy article. Controlled pre-straining operations are performed on the shape-set nitinol metal to achieve non-recoverable tensile strain greater than about 0.20% at or near the surface of selected regions in the nitinol metal article. The pre-straining operations result in a significant increase in fatigue life of the selectively treated regions and an overall improvement in the fatigue performance of the device. | 12-30-2010 |
20120323298 | SHAPE MEMORY ALLOY ARTICLES WITH IMPROVED FATIGUE PERFORMANCE AND METHODS THEREFORE - Articles made of shape memory alloys having improved fatigue performance and to methods of treating articles formed from shape memory alloy materials by pre-straining the articles (or desired portions of the articles) in a controlled manner so that the resultant articles exhibit improved fatigue performance. The shape memory articles are preferably medical devices, more preferably implantable medical devices. They are most preferably devices of nitinol shape memory alloy, most particularly that is superelastic at normal body temperature. The pre-straining method of the present invention as performed on such articles includes the controlled introduction of non-recoverable tensile strains greater than about 0.20% at the surface of a desired portion of a shape memory alloy article. Controlled pre-straining operations are performed on the shape-set nitinol metal to achieve non-recoverable tensile strain greater than about 0.20% at or near the surface of selected regions in the nitinol metal article. | 12-20-2012 |
20140207228 | SHAPE MEMORY ALLOY ARTICLES WITH IMPROVED FATIGUE PERFORMANCE AND METHODS THEREFORE - Articles made of shape memory alloys having improved fatigue performance and to methods of treating articles formed from shape memory alloy materials by pre-straining the articles (or desired portions of the articles) in a controlled manner so that the resultant articles exhibit improved fatigue performance. The shape memory articles are preferably medical devices, more preferably implantable medical devices. They are most preferably devices of nitinol shape memory alloy, most particularly that is superelastic at normal body temperature. The pre-straining method of the present invention as performed on such articles includes the controlled introduction of non-recoverable tensile strains greater than about 0.20% at the surface of a desired portion of a shape memory alloy article. Controlled pre-straining operations are performed on the shape-set nitinol metal to achieve non-recoverable tensile strain greater than about 0.20% at or near the surface of selected regions in the nitinol metal article. | 07-24-2014 |