Patent application number | Description | Published |
20080300020 | WIRELESS COMMUNICATION SYSTEM, SIM CARD, MOBILE COMMUNICATION TERMINAL, AND DATA GUARANTEEING METHOD - The loss of data stored in a secure memory card, such as a SIM card, due to the physical destruction thereof is prevented. A host unit performs card authentication of a memory card, and transmits update data for the memory card by security communication to update data when the result of the authentication is OK. Then, the host unit outputs a request for mirror-updating the card data to a base station server. When an access is permitted, the card data is transmitted to the base station server via the host unit to mirror-update the card data. When the mirror-updating of the card data is completed, the base station server returns a completion confirmation to the host unit, so that a data backup process is completed. By thus causing the base station server to mirror-update the data in the memory card, the loss of the stored data is prevented. | 12-04-2008 |
20090057417 | IC CARD - The present invention realizes a card on which a secure IC chip (a first semiconductor chip) that operates on both of a high power source voltage and a low power source voltage, and a nonvolatile semiconductor storage chip that operates on the lower power source voltage are mounted. Means for operating the card without exerting an adverse influence of the nonvolatile semiconductor storage chip when the high power source voltage is supplied is realized. A card has a voltage supply interrupting unit which is coupled to a power source terminal to which a first power source voltage and a second power source voltage higher than the first power source voltage are supplied, and a grounding terminal to which a grounding voltage is supplied. The voltage supply interrupting unit, when the first power source voltage is supplied, supplies voltage to a nonvolatile semiconductor storage chip and, when the second power source voltage is supplied, stops supplying the voltage to the nonvolatile semiconductor storage chip. | 03-05-2009 |
20090152709 | SEMICONDUCTOR DEVICE - A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer. | 06-18-2009 |
20090200680 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 08-13-2009 |
20100072284 | SEMICONDUCTOR DEVICE AND ADAPTOR FOR THE SAME - Connector terminals are arranged at the center of a thin memory card | 03-25-2010 |
20100148350 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate. | 06-17-2010 |
20110037170 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFOR - Reduction of the size of and enhancement of the reliability, mounting strength, and mounting reliability of a semiconductor module are achieved. The semiconductor module includes: a wiring substrate; an electronic component placed over the upper surface of the wiring substrate; an electronic component placed over the under surface of the wiring substrate; a lead placed over the under surface of the wiring substrate; and encapsulation resin covering the under surface of the wiring substrate including the electronic component and the lead. The lead includes: a first portion coupled to an electrode pad via a joining material; a second portion bent from the first portion; and a third portion bent from the second portion. The third portion is positioned closer to the peripheral edge portion side of the under surface of the wiring substrate than the first portion. At the same time, the third portion is arranged at a position farther from the under surface of the wiring substrate than the first portion. The third portion of the lead is exposed from the main surface and side surface of the encapsulation resin and functions as a terminal for external coupling. | 02-17-2011 |
20110140285 | Semiconductor Device - A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer. | 06-16-2011 |
20110156229 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged. | 06-30-2011 |
20110233788 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 09-29-2011 |
20130069249 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 03-21-2013 |
20140347809 | SEMICONDUCTOR DEVICE - A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card. | 11-27-2014 |